Brother International HL-2600CN Service Manual - Page 95
Cache memory: 32KB Command cache / 32KB Data cache, External interfaces Centronics, BR-NET, IDE
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2.3.2 Circuit (1) CPU block Model name: TMPR4955AF-266, MIPS 64bit RISC CPU manufactured by TOSHIBA Clock speed: 66.7MHz (external) / 266MHz (internal) Cache memory: 32KB (Command cache) / 32KB (Data cache) Bus width: 32bit (external) / 64bit (internal) Internal Floating Point Unit (FPU) Appearance: 160-pin QFP (2) ASIC block Model name: MF87F4561 manufactured by Fujitsu Appearance: 420pin BGA Functions: Controls CPU Controls memory Controls interrupts Timer External interfaces (Centronics, BR-NET, IDE, Compact Flash, USB) Engine interface (Video signal control) Supports Software (3) Gate Array block Model name: Appearance: Functions: SLAC099HF1A manufactured by Epson 160pin QFP Engine control (4) ROM block The ROM stores the CPU control program and font data. ROMs used are an 16Mbytes masked ROM, and an 8 Mbytes flash ROM which can be rewritten on the board. Access time: Appearance: Model name: Access time: Appearance: less than 100nsec. (page access: less than 30nsec) 48pin TSOP MBM29DL32BD-90 manufactured by Fujitsu less than 90nsec. 48-pin TSOP IV-44