Intel BX80601920 Data Sheet - Page 19

Datasheet

19

Electrical Specifications

Notes:

1.

Unless otherwise specified, signals have ODT in the package with 50



pulldown to V

SS

.

2.

PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35



pullup to V

TT

.

3.

VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 k



to 20 k



pulldown

to V

SS

.

4.

TRST# has ODT in package with a 1 k



to 5 k



pullup to V

TT

.

5.

All DDR signals are terminated to VDDQ/2

6.

DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

7.

While TMS and TDI do not have On-Die Termination, these signals are weakly pulled up using a 1–5 k



resistor to V

TT

8.

While TCK does not have On-Die Termination, this signal is weakly pulled down using a 1–5 k



resistor to

V

SS

.

All Control Sideband Asynchronous signals are required to be asserted/de-asserted for

at least eight BCLKs for the processor to recognize the proper signal state. See

Section 2.11

for the DC specifications. See

Chapter 6

for additional timing

requirements for entering and leaving the low power states.

2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor be first in the TAP chain and followed by

any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of

accepting an input of the appropriate voltage. Two copies of each signal may be

required with each driving a different voltage level.

Single ended

CMOS Output

VTT_VID[4:2]

Single ended

Analog Input

ISENSE

Reset Signal

Single ended

Reset Input

RESET#

PWRGOOD Signals

Single ended

Asynchronous Input

VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD

Power/Other

Power

VCC, VTTA, VTTD, VCCPLL, VDDQ

Asynchronous CMOS Output

PSI#

Sense Points

VCC_SENSE, VSS_SENSE

Other

SKTOCC#, DBR#

Notes:

1.

Refer to

Chapter 5

for signal descriptions.

2.

DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

Table 2-4.

Signals with ODT

•

QPI_DRX_DP[19:0], QPI_DRX_DN[19:0], QPI_DTX_DP[19:0], QPI_DTX_DN[19:0], QPI_CLKRX_D[N/P],

QPI_CLKTX_D[N/P]

•

DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][7:0], DDR{0/1/2}_PAR_ERR#[0:2], VDDPWRGOOD

•

BCLK_ITP_D[N/P]

•

PECI

•

BPM#[7:0], PREQ#, TRST#, VCCPWRGOOD, VTTPWRGOOD

Table 2-3.

Signal Groups (Sheet 2 of 2)

Signal Group

Type

Signals

1,2

Section	Page
Contents	3
Figures	4
Tables	5
Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series Features	7
Revision History	8
1 Introduction	9
1.1 Terminology	10
1.2 References	11
2 Electrical Specifications	13
2.1 Intel® QPI Differential Signaling	13
2.2 Power and Ground Lands	13
2.3 Decoupling Guidelines	13
2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling	14
2.4 Processor Clocking (BCLK_DP, BCLK_DN)	14
2.4.1 PLL Power Supply	14
2.5 Voltage Identification (VID)	14
2.6 Reserved or Unused Signals	17
2.7 Signal Groups	18
2.8 Test Access Port (TAP) Connection	19
2.9 Platform Environmental Control Interface (PECI) DC Specifications	20
2.9.1 DC Characteristics	20
2.9.2 Input Device Hysteresis	21
2.10 Absolute Maximum and Minimum Ratings	21
2.11 Processor DC Specifications	22
2.11.1 DC Voltage and Current Specification	23
2.11.2 VCC Overshoot Specification	29
2.11.3 Die Voltage Validation	30
3 Package Mechanical Specifications	31
3.1 Package Mechanical Drawing	31
3.2 Processor Component Keep-Out Zones	34
3.3 Package Loading Specifications	34
3.4 Package Handling Guidelines	34
3.5 Package Insertion Specifications	34
3.6 Processor Mass Specification	35
3.7 Processor Materials	35
3.8 Processor Markings	35
3.9 Processor Land Coordinates	36
4 Land Listing	37
5 Signal Descriptions	67
6 Thermal Specifications	71
6.1 Package Thermal Specifications	71
6.1.1 Thermal Specifications	71
6.1.2 Thermal Metrology	75
6.2 Processor Thermal Features	76
6.2.1 Processor Temperature	76
6.2.2 Adaptive Thermal Monitor	76
6.2.3 THERMTRIP# Signal	79
6.3 Platform Environment Control Interface (PECI)	79
6.3.1 Introduction	79
6.3.2 PECI Specifications	81
6.4 Storage Conditions Specifications	82
7 Features	83
7.1 Power-On Configuration (POC)	83
7.2 Clock Control and Low Power States	83
7.2.1 Thread and Core Power State Descriptions	84
7.2.2 Package Power State Descriptions	85
7.3 Sleep States	86
7.4 ACPI P-States (Intel® Turbo Boost Technology)	86
7.5 Enhanced Intel® SpeedStep® Technology	87
8 Boxed Processor Specifications	89
8.1 Introduction	89
8.2 Mechanical Specifications	90
8.2.1 Boxed Processor Cooling Solution Dimensions	90
8.2.2 Boxed Processor Fan Heatsink Weight	92
8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	92
8.3 Electrical Requirements	92
8.3.1 Fan Heatsink Power Supply	92
8.4 Thermal Specifications	93
8.4.1 Boxed Processor Cooling Requirements	93

Intel BX80601920 Data Sheet - Page 19

Test Access Port TAP Connection

Page 19 highlights