Intel BX80601920 Data Sheet - Page 86

Features

86

Datasheet

If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and

for processors with an integrated memory controller, the DRAM will be put into self-

refresh.

7.2.2.4

Package C6 State

The package will enter the C6 low power state when all cores are in the C6 or lower

power state and the processor has been granted permission by the other component(s)

in the system to enter the C6 state. The package will also enter the C6 state when all

cores are in an idle state lower than C6 but the other component(s) have only granted

permission to enter C6.

If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and

the shared cache will enter a deep sleep state. Additionally, for processors with an

integrated memory controller, the DRAM will be put into self-refresh.

7.3

Sleep States

The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in

Table 7-3

. For information on ACPI S-states and related terminology, refer to ACPI

Specification. The S-state transitions are coordinated by the processor in response PM

Request (PMReq) messages from the chipset. The processor itself will never request a

particular S-state.

Notes:

1.

If the chipset requests an S-state transition, which is not allowed, a machine check error

will be generated by the processor.

7.4

ACPI P-States (Intel

®

Turbo Boost Technology)

The processor supports ACPI P-States. A new feature is that the P0 ACPI state will be a

request for Intel Turbo Boost Technology. This technology opportunistically and

automatically allows the processor to run faster than its marked frequency if the

processor is operating below power, thermal, and current specifications. Maximum

turbo frequency is dependant on the processor component and number of active cores.

No special hardware support is necessary for Intel Turbo Boost Technology. BIOS and

the operating system can enable or disable Intel Turbo Boost Technology.

Table 7-3.

Processor S-States

S-State

Power Reduction

Allowed Transitions

S0

Normal Code Execution

S1 (using PMReq)

S1

Cores in C1E like state, processor responds with

CmpD(S1) message.

S0 (using reset or PMReq)

S3, S4 (using PMReq)

S3

Memory put into self-refresh, processor responds with

CmpD(S3) message.

S0 (using reset)

S4/S5

Processor responds with CmpD(S4/S5) message.

S0 (using reset)

Section	Page
Contents	3
Figures	4
Tables	5
Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series Features	7
Revision History	8
1 Introduction	9
1.1 Terminology	10
1.2 References	11
2 Electrical Specifications	13
2.1 Intel® QPI Differential Signaling	13
2.2 Power and Ground Lands	13
2.3 Decoupling Guidelines	13
2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling	14
2.4 Processor Clocking (BCLK_DP, BCLK_DN)	14
2.4.1 PLL Power Supply	14
2.5 Voltage Identification (VID)	14
2.6 Reserved or Unused Signals	17
2.7 Signal Groups	18
2.8 Test Access Port (TAP) Connection	19
2.9 Platform Environmental Control Interface (PECI) DC Specifications	20
2.9.1 DC Characteristics	20
2.9.2 Input Device Hysteresis	21
2.10 Absolute Maximum and Minimum Ratings	21
2.11 Processor DC Specifications	22
2.11.1 DC Voltage and Current Specification	23
2.11.2 VCC Overshoot Specification	29
2.11.3 Die Voltage Validation	30
3 Package Mechanical Specifications	31
3.1 Package Mechanical Drawing	31
3.2 Processor Component Keep-Out Zones	34
3.3 Package Loading Specifications	34
3.4 Package Handling Guidelines	34
3.5 Package Insertion Specifications	34
3.6 Processor Mass Specification	35
3.7 Processor Materials	35
3.8 Processor Markings	35
3.9 Processor Land Coordinates	36
4 Land Listing	37
5 Signal Descriptions	67
6 Thermal Specifications	71
6.1 Package Thermal Specifications	71
6.1.1 Thermal Specifications	71
6.1.2 Thermal Metrology	75
6.2 Processor Thermal Features	76
6.2.1 Processor Temperature	76
6.2.2 Adaptive Thermal Monitor	76
6.2.3 THERMTRIP# Signal	79
6.3 Platform Environment Control Interface (PECI)	79
6.3.1 Introduction	79
6.3.2 PECI Specifications	81
6.4 Storage Conditions Specifications	82
7 Features	83
7.1 Power-On Configuration (POC)	83
7.2 Clock Control and Low Power States	83
7.2.1 Thread and Core Power State Descriptions	84
7.2.2 Package Power State Descriptions	85
7.3 Sleep States	86
7.4 ACPI P-States (Intel® Turbo Boost Technology)	86
7.5 Enhanced Intel® SpeedStep® Technology	87
8 Boxed Processor Specifications	89
8.1 Introduction	89
8.2 Mechanical Specifications	90
8.2.1 Boxed Processor Cooling Solution Dimensions	90
8.2.2 Boxed Processor Fan Heatsink Weight	92
8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	92
8.3 Electrical Requirements	92
8.3.1 Fan Heatsink Power Supply	92
8.4 Thermal Specifications	93
8.4.1 Boxed Processor Cooling Requirements	93

Intel BX80601920 Data Sheet - Page 86

Sleep States, ACPI P-States Intel, Turbo Boost Technology

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