Intel BX80601920 Data Sheet - Page 87

Enhanced Intel, SpeedStep, Technology

Page 87 highlights

Features 7.5 Enhanced Intel® SpeedStep® Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power. • Voltage and frequency selection is software controlled by writing to processor MSRs: - If in the target frequency is higher than steps by placing new values on the tVhIeDcpuirnrsenatnfdretqhueePnLcLy,thVeCnC is ramped up locks to the new frequency. - If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism. - Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition completes. • The processor controls voltage ramp rates internally to ensure smooth transitions. • Low transition latency and large number of transitions possible per second: - Processor core (including shared cache) is unavailable for less than 5 µs during the frequency transition. § Datasheet 87

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Datasheet
87
Features
7.5
Enhanced Intel
®
SpeedStep
®
Technology
The processor features Enhanced Intel SpeedStep Technology. Following are the key
features of Enhanced Intel SpeedStep Technology:
Multiple voltage and frequency operating points provide optimal performance at the
lowest power.
Voltage and frequency selection is software controlled by writing to processor
MSRs:
If the target frequency is higher than the current frequency, V
CC
is ramped up
in steps by placing new values on the VID pins and the PLL then locks to the
new frequency.
If the target frequency is lower than the current frequency, the PLL locks to the
new frequency and the V
CC
is changed through the VID pin mechanism.
Software transitions are accepted at any time. If a previous transition is in
progress, the new transition is deferred until the previous transition completes.
The processor controls voltage ramp rates internally to ensure smooth transitions.
Low transition latency and large number of transitions possible per second:
Processor core (including shared cache) is unavailable for less than 5 μs during
the frequency transition.
§