AMD AMD-K6-2/400 User Guide - Page 135
HIT# (Inquire Cycle Hit), 5.25 HITM# (Inquire Cycle Hit To Modified Line
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.24 HIT# (Inquire Cycle Hit) Pin Attribute Summary Driven Output The processor asserts HIT# during an inquire cycle to indicate that the cache line is valid within the processor's L1 and/or L2 caches (also known as a cache hit). The cache line can be in the modified, exclusive, or shared state. HIT# is always driven-except in the Three-State Test mode- and only changes state the clock edge after the clock edge on which EADS# is sampled asserted. It is driven in the same state until the next inquire cycle. 5.25 HITM# (Inquire Cycle Hit To Modified Line) Pin Attribute Summary Output The processor asserts HITM # during an inquire cycle to indicate that the cache line exists in the processor's L1 data cache or L2 cache in the modified state. The processor performs a writeback cycle as a result of this cache hit. If an inquire cycle hits a cache line that is currently being written back, the processor asserts HITM # but does not execute another writeback cycle. The system logic must not expect the processor to assert ADS# each time HITM# is asserted. Driven HITM # is always driven - except in the Three-State Test mode-and, in particular, is driven to represent the result of an inquire cycle the clock edge after the clock edge on which EADS# is sampled asserted. If HITM# is negated in response to the inquire address, it remains negated until the next inquire cycle. If HITM# is asserted in response to the inquire address, it remains asserted throughout the writeback cycle and is negated one clock edge after the last BRDY # of the writeback is sampled asserted. Chapter 5 Signal Descriptions 113