Home » AMD Manuals » Processors » AMD AMD-K6-2/400 » Manual Viewer

AMD AMD-K6-2/400 User Guide - Page 350

Table 77., OBGA Pin Designations by Functional Grouping, Pin Name, Control, Address, Parity

Add to My Manuals
Save this manual to your list of manuals

Page 350 highlights

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 77. OBGA Pin Designations by Functional Grouping Pin Name Pin Number Control A20M# W4 ADS# U1 ADSC# T3 AHOLD K4 APCHK# R1 BE0# U6 BE1# W5 BE2# V6 BE3# W6 BE4# U7 BE5# T8 BE6# U8 BE7# V8 BF0 N17 BF1 M17 BF2 N19 BOFF# L3 BRDY# K1 BRDYC# L1 BREQ P4 CACHE# J4 CLK U9 D/C# U3 EADS# V4 EWBE# K3 FERR# G4 FLUSH# T7 HIT# W3 HITM# U4 HLDA T2 HOLD M3 IGNNE# P19 INIT P17 INTR P16 INV J1 KEN# K2 LOCK# T1 M/IO# J3 NA# L4 NMI R17 PCD R4 PCHK# P3 PWT V2 RESET W9 SCYC W8 SMI# P18 SMIACT# P2 STPCLK# M18 W/R# U5 WB/WT# M2 Pin Name Pin Number Address A3 T14 A4 T13 A5 W15 A6 V14 A7 U14 A8 T12 A9 W14 A10 V12 A11 W13 A12 W12 A13 U13 A14 W11 A15 U12 A16 T11 A17 W10 A18 V10 A19 U10 A20 T10 A21 T17 A22 T19 A23 U19 A24 T18 A25 V18 A26 U17 A27 T15 A28 R16 A29 U16 A30 V16 A31 U15 Pin Name Pin Number Data D0 H18 D1 G19 D2 H19 D3 F17 D4 H17 D5 F18 D6 F19 D7 E16 D8 E17 D9 E19 D10 D19 D11 F16 D12 D18 D13 D14 D14 D17 D15 D15 D16 A17 D17 B18 D18 C19 D19 B16 D20 A16 D21 D13 D22 C16 D23 A15 D24 C14 D25 C13 D26 A14 D27 C12 D28 A13 D29 A12 D30 B12 D31 D11 D32 B10 D33 A10 D34 D10 D35 C10 D36 D9 D37 A9 D38 C9 D39 A8 D40 A7 D41 B8 D42 D7 D43 C7 D44 B6 D45 A6 D46 C6 D47 A5 D48 D6 D49 C5 D50 C4 D51 B2 Pin Name Pin Number Data D52 A3 D53 D5 D54 C3 D55 E3 D56 D2 D57 E4 D58 D3 D59 D1 D60 E1 D61 F3 D62 F2 D63 F4 Test TCK TDI TDO TMS TRST# AP DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 J19 K19 J16 K18 K17 Parity R3 G17 C17 B14 C11 C8 A4 C1 F1 Voltage ID1 VID0 W17 VID1 W16 VID2 L19 VID3 C15 VID4 A11 Notes: 1. The VID[4:0] pins are supported on low-power versions only. These pins are defined as no-connects on standard-power versions. 328 Pin Designations Chapter 18

Section	Page
IF YOU HAVE QUESTIONS, WE\	3
Contents	5
List of Figures	9
List of Tables	13
Revision History	17
About this Data Sheet	19
1 AMDK6™2E+ Embedded Processor	23
1.1 AMDK6™2E+ Embedded Processor Features	25
1.2 Process Technology	29
1.3 Super7™ Platform	30
2 Internal Architecture	33
2.1 Microarchitecture Overview	33
2.2 Cache, Instruction Prefetch, and Predecode Bits	38
2.3 Instruction Fetch and Decode	39
2.4 Centralized Scheduler	43
2.5 Execution Units	44
2.6 BranchPrediction Logic	47
3 Software Environment	49
3.1 Registers	49
3.2 ModelSpecific Registers (MSR)	66
3.3 Memory Management Registers	76
3.4 Paging	78
3.5 Descriptors and Gates	81
3.6 Exceptions and Interrupts	84
3.7 Instructions Supported by the AMDK6™2E+ Processor	85
4 Logic Symbol Diagram	113
5 Signal Descriptions	115
5.1 Signal Terminology	115
5.2 A20M# (Address Bit 20 Mask)	116
5.3 A[31:3] (Address Bus)	117
5.4 ADS# (Address Strobe)	118
5.5 ADSC# (Address Strobe Copy)	118
5.6 AHOLD (Address Hold)	119
5.7 AP (Address Parity)	120
5.8 APCHK# (Address Parity Check)	121
5.9 BE[7:0]# (Byte Enables)	122
5.10 BF[2:0] (Bus Frequency)	123
5.11 BOFF# (Backoff)	124
5.12 BRDY# (Burst Ready)	125
5.13 BRDYC# (Burst Ready Copy)	126
5.14 BREQ (Bus Request)	126
5.15 CACHE# (Cacheable Access)	127
5.16 CLK (Clock)	127
5.17 D/C# (Data/Code)	128
5.18 D[63:0] (Data Bus)	129
5.19 DP[7:0] (Data Parity)	130
5.20 EADS# (External Address Strobe)	131
5.21 EWBE# (External Write Buffer Empty)	132
5.22 FERR# (FloatingPoint Error)	133
5.23 FLUSH# (Cache Flush)	134
5.24 HIT# (Inquire Cycle Hit)	135
5.25 HITM# (Inquire Cycle Hit To Modified Line)	135
5.26 HLDA (Hold Acknowledge)	136
5.27 HOLD (Bus Hold Request)	137
5.28 IGNNE# (Ignore Numeric Exception)	138
5.29 INIT (Initialization)	139
5.30 INTR (Maskable Interrupt)	140
5.31 INV (Invalidation Request)	140
5.32 KEN# (Cache Enable)	141
5.33 LOCK# (Bus Lock)	142
5.34 M/IO# (Memory or I/O)	143
5.35 NA# (Next Address)	144
5.36 NMI (NonMaskable Interrupt)	145
5.37 PCD (Page Cache Disable)	146
5.38 PCHK# (Parity Check)	147
5.39 PWT (Page Writethrough)	148
5.40 RESET (Reset)	149
5.41 RSVD (Reserved)	150
5.42 SCYC (Split Cycle)	151
5.43 SMI# (System Management Interrupt)	152
5.44 SMIACT# (System Management Interrupt Active)	153
5.45 STPCLK# (Stop Clock)	154
5.46 TCK (Test Clock)	155
5.47 TDI (Test Data Input)	155
5.48 TDO (Test Data Output)	155
5.49 TMS (Test Mode Select)	156
5.50 TRST# (Test Reset)	156
5.51 VCC2DET (VCC2 Detect)	157
5.52 VCC2H/L# (VCC2 High/Low)	158
5.53 VID[4:0] (Voltage Identification)	159
5.54 W/R# (Write/Read)	160
5.55 WB/WT# (Writeback or Writethrough)	161
5.56 Pin Tables by Type	162
5.57 Bus Cycle Definitions	164
6 AMD PowerNow!™ Technology	165
6.1 Enhanced Power Management Features	165
6.2 Dynamic Core Frequency and Core Voltage Control	172
7 Bus Cycles	175
7.1 Timing Diagrams	175
7.2 Bus States	177
7.3 Memory Reads and Writes	180
7.4 I/O Read and Write	188
7.5 Inquire and Bus Arbitration Cycles	190
7.6 Special Bus Cycles	212
8 Poweron Configuration and Initialization	221
8.1 Signals Sampled During the Falling Transition of RESET	221
8.2 RESET Requirements	222
8.3 State of Processor After RESET	222
8.4 State of Processor After INIT	225
9 Cache Organization	227
9.1 MESI States in the L1 Data Cache and L2 Cache	229
9.2 Predecode Bits	230
9.3 Cache Operation	230
9.4 Cache Disabling and Flushing	233
9.5 L2 Cache Testing	235
9.6 CacheLine Fills	235
9.7 CacheLine Replacements	236
9.8 Write Allocate	237
9.9 Prefetching	242
9.10 Cache States	243
9.11 Cache Coherency	244
9.12 Writethrough and Writeback Coherency States	249
9.13 A20M# Masking of Cache Accesses	249
10 Write Merge Buffer	251
10.1 EWBE# Control	251
10.2 Memory Type Range Registers	253
10.3 Memory-Range Restrictions	255
10.4 Examples	257
11 FloatingPoint and Multimedia Execution Units	259
11.1 FloatingPoint Execution Unit	259
11.2 Multimedia and 3DNow!™ Execution Units	261
11.3 FloatingPoint and MMX™/3DNow!™ Instruction Compatibility	262
12 System Management Mode (SMM)	263
12.1 SMM Operating Mode and Default Register Values	263
12.2 SMM StateSave Area	265
12.3 SMM Revision Identifier	267
12.4 SMM Base Address	268
12.5 Halt Restart Slot	268
12.6 I/O Trap Doubleword	269
12.7 I/O Trap Restart Slot	270
12.8 Exceptions, Interrupts, and Debug in SMM	272
13 Test and Debug	273
13.1 BuiltIn SelfTest (BIST)	273
13.2 ThreeState Test Mode	274
13.3 BoundaryScan Test Access Port (TAP)	275
13.4 Cache Inhibit	285
13.5 L2 Cache and Tag Array Testing	286
13.6 Debug	290
14 Clock Control	297
14.1 Clock Control States	297
14.2 Halt State	300
14.3 Stop Grant State	300
14.4 Stop Grant Inquire State	302
14.5 EPM Stop Grant State	303
14.6 Stop Clock State	305
15 Electrical Data	307
15.1 Operating Ranges	308
15.2 Absolute Ratings	309
15.3 DC Characteristics	309
15.4 Power Dissipation	311
15.5 Power and Grounding	313
16 Signal Switching Characteristics	317
16.1 CLK Switching Characteristics	318
16.2 Clock Switching Characteristics for 100MHz Bus Operation	318
16.3 Clock Switching Characteristics for 66MHz Bus Operation	319
16.4 Valid Delay, Float, Setup, and Hold Timings	320
16.5 Output Delay Timings for 100MHz Bus Operation	320
16.6 Input Setup and Hold Timings for 100MHz Bus Operation	322
16.7 Output Delay Timings for 66MHz Bus Operation	324
16.8 Input Setup and Hold Timings for 66MHz Bus Operation	326
16.9 RESET and Test Signal Timing	328
16.10 Timing Diagrams	331
17 Thermal Design	335
17.1 Package Thermal Specifications	335
17.2 Measuring Case Temperature	339
17.3 Layout and Airflow Considerations	339
18 Pin Designations	343
18.1 Pins Designations for CPGA Package	344
18.2 Pins Designations for OBGA Package	348
19 Package Specifications	353
19.1 321Pin Staggered CPGA Package Specification	353
19.2 349Ball OBGA Package Specification	354
20 Ordering Information	355

Match case Limit results 1 per page

328

Pin Designations

Chapter 18

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Preliminary Information

Notes: 1. The VID[4:0] pins are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.

Table 77.

OBGA Pin Designations by Functional Grouping

Pin Name

Pin Number

Pin Name

Pin Number

Pin Name

Pin Number

Pin Name

Pin Number

Control

Address

Data

A20M#

T14

H18

D52

ADS#

T13

G19

D53

ADSC#

W15

H19

D54

AHOLD

V14

F17

D55

APCHK#

U14

H17

D56

BE0#

T12

F18

D57

BE1#

W14

F19

D58

BE2#

A10

V12

E16

D59

BE3#

A11

W13

E17

D60

BE4#

A12

W12

E19

D61

BE5#

A13

U13

D10

D19

D62

BE6#

A14

W11

D11

F16

D63

BE7#

A15

U12

D12

D18

Test

BF0

N17

A16

T11

D13

D14

TCK

J19

BF1

M17

A17

W10

D14

D17

TDI

K19

BF2

N19

A18

V10

D15

TDO

J16

BOFF#

A19

U10

D16

A17

TMS

K18

BRDY#

A20

T10

D17

B18

TRST#

K17

BRDYC#

A21

T17

D18

C19

Parity

BREQ

A22

T19

D19

B16

CACHE#

A23

U19

D20

A16

DP0

G17

CLK

A24

T18

D21

D13

DP1

C17

D/C#

A25

V18

D22

C16

DP2

B14

EADS#

A26

U17

D23

A15

DP3

C11

EWBE#

A27

T15

D24

C14

DP4

FERR#

A28

R16

D25

C13

DP5

FLUSH#

A29

U16

D26

A14

DP6

HIT#

A30

V16

D27

C12

DP7

HITM#

A31

U15

D28

A13

Voltage ID

HLDA

D29

A12

VID0

W17

HOLD

D30

B12

VID1

W16

IGNNE#

P19

D31

D11

VID2

L19

INIT

P17

D32

B10

VID3

C15

INTR

P16

D33

A10

VID4

A11

INV

D34

D10

KEN#

D35

C10

LOCK#

D36

M/IO#

D37

NA#

D38

NMI

R17

D39

PCD

D40

PCHK#

D41

PWT

D42

RESET

D43

SCYC

D44

SMI#

P18

D45

SMIACT#

D46

STPCLK#

M18

D47

W/R#

D48

WB/WT#

D49

D50

D51