AMD AMD-K6-2/400 User Guide - Page 303
EPM Stop Grant State, Enter EPM Stop Grant, State
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 14.5 EPM Stop Grant State Enter EPM Stop Grant State This state is supported on the low-power versions of the AMD-K6-2E+ processor. After receiving a write of a non-zero value to the SGTC (Stop Grant Time-out Counter) field located within the EPM 16-byte I/O block, the processor flushes its instruction pipelines, completes all pending and in-progress bus cycles, and performs the following: s Drives the processor VID[4:0] output pins to the value stored in the VIDO field of the EPM 16-byte I/O block (see "EPM 16-Byte I/O Block" on page 146) if the VIDC bit is set to 1. s Forwards the processor-to-bus clock ratio stored in the IBF[2:0] field of the EPM 16-byte I/O block to the internal PLL if the BDC[1:0] value is set to 1xb. The EPM Stop Grant state is like the Halt state in that the processor disables most of its internal clock distribution in the EPM Stop Grant state. In order to support the following operations, the internal PLL still runs, and some internal resources are still clocked in the EPM Stop Grant state. s Time Stamp Counter (TSC): The TSC continues to count in the EPM Stop Grant state. s Signal Sampling: The processor continues to sample INIT, INTR, NMI, RESET, and SMI#. Unlike the Halt and Stop Grant states, system-initiated inquire cycles are not supported and must be prevented during the EPM Stop Grant state. FLUSH# is not recognized in the EPM Stop Grant state (unlike while in the Halt state). Upon entering the EPM Stop Grant state, all signals driven by the processor retain their state as they existed following the completion of the EPM Stop Grant special cycle. Exit EPM Stop Grant State The processor remains in the EPM Stop Grant state until the allotted time expires, as determined by the value written to the SGTC field, or until RESET is sampled asserted. Once the allotted time expires, the processor returns to the Normal state. After the transition to the Normal state, the processor resumes execution at the instruction boundary on which the EPM Stop Grant state was entered. Chapter 14 Clock Control 281