AMD AMD-K6-2/400 User Guide - Page 68
Test Register 12, Time Stamp Counter, EDX-Upper 32 bits of TSC
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Test Register 12 (TR12) 63 Reserved Test register 12 provides a method for disabling the L1 caches. Figure 32 shows the format of TR12. The TR12 register is MSR 0Eh. 43 2 1 0 C I Symbol Description Bit CI Cache Inhibit Bit 3 Figure 32. Test Register 12 (TR12) Time Stamp Counter 63 With each processor clock cycle, the processor increments the 64-bit time stamp counter (TSC) MSR. Figure 33 shows the format of the TSC. The TSC register is MSR 10h. The counter can be written or read using the WRMSR or RDMSR instructions when the ECX register contains the value 10h and CPL = 0. The counter can also be read using the RDTSC instruction, but the procedure must be executing at privilege level 0 for the RDTSC instruction to execute. This condition is reflected by the status of the Time Stamp Disable (TSD) bit in CR4. With either of these instructions, the EDX and EAX registers hold the upper and lower dwords of the 64-bit value to be written to or read from the TSC, as follows: s EDX-Upper 32 bits of TSC s EAX-Lower 32 bits of TSC The TSC can be loaded with any arbitrary value. This feature is compatible with the Pentium processor. 0 TSC Figure 33. Time Stamp Counter (TSC) 46 Software Environment Chapter 3