AMD AMD-K6-2/400 User Guide - Page 286

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 initiated by the system logic, including the execution of writeback cycles when a modified cache line is hit. While the L1 and L2 are inhibited, the processor continues to drive the PCD output signal appropriately, which system logic can use to control external L3 caching. In order to completely disable the L1 and L2 caches so that no valid lines exist in the cache, the Cache Inhibit bit must be set to 1 and the cache must be flushed in one of the following ways: s Asserting the FLUSH# input signal s Executing the WBINVD instruction s Executing the INVD instruction (modified cache lines are not written back to memory) s Using the Page Flush/Invalidate Register (PFIR) (see "Page Flush/Invalidate Register (PFIR)" on page 223) 13.5 L2 Cache and Tag Array Testing Level-2 Cache Array Access Register (L2AAR) The AMD-K6-2E+ processor provides the Level-2 Cache Array Access Register (L2AAR) that allows for direct access to the L2 cache and L2 tag arrays. The 128-Kbyte L2 cache in the AMD-K6-2E+ is organized as shown in Figure 91 on page 265: s Four 32-Kbyte ways s Each way contains 512sets s Each set contains four 64-byte sectors (one sector in each way) s Each sector contains two 32-byte cache lines s Each cache line contains four 8-byte octets s Each octet contains an upper and lower dword (4 bytes) Each line within a sector contains its own MESI state bits, and associated with each sector is a tag and LRU (least recently used) information. 264 Test and Debug Chapter 13