AMD AMD-K6-2/400 User Guide - Page 189
Misaligned I/O Read, and Write, Misaligned I/O Transfer, Table 31.
View all AMD AMD-K6-2/400 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 189 highlights
23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Misaligned I/O Read and Write Table 31 shows the misaligned I/O read and write cycle order executed by the AMD-K6-2E+ processor. In Figure 65, the least-significant bytes (LSBs) are transferred first. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to transfer the most-significant bytes (MSBs) to complete the misaligned bus cycle. Table 31. Bus-Cycle Order During Misaligned I/O Transfers Type of Access I/O Read I/O Write First Cycle LSBs LSBs Second Cycle MSBs MSBs CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# SCYC D[63:0] BRDY# Misaligned I/O Read Misaligned I/O Write ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE LSB MSB LSB MSB Figure 65. Misaligned I/O Transfer Chapter 7 Bus Cycles 167