AMD AMD-K6-2/400 User Guide - Page 76
Memory Management Registers, Table 8.
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 3.3 Memory Management Registers The AMD-K6-2E+ processor controls segmented memory management with the registers listed in Table 8. Figure 44 shows the formats of these registers. Table 8. Memory Management Registers Register Name Global Descriptor Table Register Interrupt Descriptor Table Register Local Descriptor Table Register Task Register Function Contains a pointer to the base of the global descriptor table Contains a pointer to the base of the interrupt descriptor table Contains a pointer to the local descriptor table of the current task Contains a pointer to the task state segment of the current task Global and Interrupt Descriptor Table Registers 47 16 15 0 32-Bit Linear Base Address 16-Bit Limit Local Descriptor Table Register and Task Register 15 0 Selector 63 32-Bit Linear Base Address 32 31 0 32-Bit Limit 15 0 Attributes Figure 44. Memory Management Registers 54 Software Environment Chapter 3