AMD AMD-K6-2/400 User Guide - Page 138
IGNNE# (Ignore Numeric Exception), Pin Attribute, Summary
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.28 IGNNE# (Ignore Numeric Exception) Pin Attribute Input Summary IGNNE#, in conjunction with the numeric error (NE) bit in the CR0 register, is used by the system logic to control the effect of a n u n m a s ke d f l o a t i n g -p o i n t ex c e p t i o n o n a p rev i o u s f l o a t i n g -p o i n t i n s t r u c t i o n d u r i n g t h e ex e c u t i o n o f a f l oa t i n g -po i n t i n st r u c ti on , MMX i n st r u c t i on , 3D N ow ! instruction, or the WAIT instruction-hereafter referred to as the target instruction. If an unmasked floating-point exception is pending and the target instruction is considered error-sensitive, then the relationship between NE and IGNNE# is as follows: s If NE = 0, then: • If IGNNE# is sampled asserted, the processor ignores the floating-point exception and continues with the execution of the target instruction. • If IGNNE# is sampled negated, the processor waits until it samples IGNNE#, INTR, SMI#, NMI, or INIT asserted. • If IGNNE# is sampled asserted while waiting, the processor ignores the floating-point exception and continues with the execution of the target instruction. • If INTR, SMI#, NMI, or INIT is sampled asserted while waiting, the processor handles its assertion appropriately. s If NE = 1, the processor invokes the INT 10h exception handler. If an unmasked floating-point exception is pending and the target instruction is considered error-insensitive, then the processor ignores the floating-point exception and continues with the execution of the target instruction. FERR # is not affected by the state of the NE bit or IGNNE #. FERR # is always asserted at the instruction boundary of the target instruction that follows the floating-point instruction that caused the unmasked floating-point exception. 116 Signal Descriptions Chapter 5