AMD AMD-K6-2/400 User Guide - Page 169
Bus Divisor and Voltage ID Control BVC Field, Table 27., Description, Function
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 31 12 11 10 9 8 7 54 0 BV SGTC V C I D BDC IBF[2:0] VIDO MC Symbol SGTC BVCM VIDC BDC IBF[2:0] VIDO Reserved Description Stop Grant Time-out Counter Bus Divisor and VID Change Mode Voltage ID Control Bus Divisor Control Internal BF Divisor Voltage ID Output Bits 31-12 11 10 9-8 7-5 4-0 Figure 56. Bus Divisor and Voltage ID Control (BVC) Field Table 27. Bus Divisor and Voltage ID Control (BVC) Definition Bit Description R/W Function1 31-12 Stop Grant Time-Out Counter (SGTC) Writing a non-zero value to this field causes the processor to enter the W EPM Stop Grant state internally. This 20-bit value is multiplied by 4096 to determine the duration of the EPM Stop Grant state, measured in processor bus clocks. 11 Bus Divisor and VID Change Mode (BVCM) This bit controls the mode in which the bus-divisor and the voltage control bits are allowed to change. If BVCM=0, the Bus Divisor and R/W Voltage ID changes take effect only upon entering the EPM Stop Grant state as a result of the SGTC field being programmed. BVCM=1 is reserved. 10 Voltage ID Control (VIDC) This bit controls the mode of Voltage ID control. If VIDC=0, the processor VID[4:0] pins are unchanged upon entering the EPM Stop Grant R/W state. If VIDC=1, the processor VID[4:0] pins are programmed to the VIDO value upon entering the EPM Stop Grant state. BIOS should initialize this bit to 1 during the POST routine. 9-8 Bus Divisor Control (BDC) This 2-bit field controls the mode of Bus Divisor control. If BDC[1:0]=00b, the BF[2:0] pins are sampled at the falling edge of R/W RESET. If BDC[1:0]=1xb, the IBF[2:0] field is sampled upon entering the EPM Stop Grant state. BDC[1:0]=01b is reserved. BIOS should initialize these bits to 10b during the POST routine. 7-5 Internal BF Divisor (IBF[2:0]) If BDC[1:0]=1xb, the processor EBF[2:0] field of the PSOR is proR/W grammed to the IBF[2:0] value upon entering the EPM Stop Grant state. 4-0 Voltage ID Output (VIDO) This 5-bit value is driven out on the processor VID[4:0] pins upon R/W entering the EPM Stop Grant state if the VIDC bit=1. These bits are ini- tialized to 01010b and driven on the processor VID[4:0] pins at RESET. Notes: 1. All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b. Chapter 6 AMD PowerNow!™ Technology 147