AMD AMD-K6-2/400 User Guide - Page 274
ThreeState Test Mode, Test and Debug,
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 13.2 252 The contents of the EAX general-purpose register after the completion of reset indicate if the BIST was successful. s If EAX contains 0000_0000h, then BIST was successful. s If EAX is non-zero, the BIST failed. Following the completion of the BIST, the processor jumps to address FFFF_FFF0h to start instruction execution, regardless of the outcome of the BIST. The BIST takes approximately 5,000,000 processor clocks to complete. Three-State Test Mode The Three-State Test mode causes the processor to float its output and bidirectional pins, which is useful for board-level manufacturing testing. In this mode, the processor is electrically isolated from other components on a system board, allowing automated test equipment (ATE) to test components that drive the same signals as those the processor floats. If the FLUSH# signal is sampled Low during the falling transition of RESET, the processor enters the Three-State Test mode. (See "FLUSH# (Cache Flush)" on page 112 for the specific sampling requirements.) The signals floated in the Three-State Test mode are as follows: s A[31:3] s ADS# s ADSC# s AP s APCHK# s BE[7:0]# s BREQ s CACHE# s D/C# s D[63:0] s DP[7:0] s FERR# s HIT# s HITM# s HLDA s LOCK# s M/IO# s PCD s PCHK# s PWT s SCYC s SMIACT# s VID[4:0] s W/R# The VCC2DET, VCC2H/L#, and TDO signals are the only outputs not floated in the Three-State Test mode. s VCC2DET and VCC2H/L# must remain Low to ensure the system continues to supply the specified processor core voltage to the VCC2 pins. Test and Debug Chapter 13