AMD AMD-K6-2/400 User Guide - Page 272
Exceptions, Interrupts, and Debug in SMM, NMI is recognized within SMM, NMI recognition remains
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 12.8 Exceptions, Interrupts, and Debug in SMM During an SMI# I/O trap, the exception/interrupt priority of the AMD-K6-2E+ processor changes from its normal priority. The normal priority places the debug traps at a priority higher than the sampling of the FLUSH# or SMI# signals. However, during an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals takes precedence over debug traps. The processor recognizes the assertion of NMI within SMM immediately after the completion of an IRET instruction. Once NMI is recognized within SMM, NMI recognition remains enabled until SMM is exited, at which point NMI masking is restored to the state it was in before entering SMM. 250 System Management Mode (SMM) Chapter 12