Home » AMD Manuals » Processors » AMD AMD-K6-2/400 » Manual Viewer

AMD AMD-K6-2/400 User Guide - Page 279

Test and Debug, Table 50., Boundary Scan Bit Definitions

Add to My Manuals
Save this manual to your list of manuals

Page 279 highlights

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 50. Boundary Scan Bit Definitions1 Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable 296 A6_E 263 A28_E 230 HIT# 197 AP 164 RSVD 131 D40_E 295 A6 262 A28 229 A27_E 196 A20_E 163 RSVD 130 D40 294 VID1_E2 261 ADS_E 228 A27 195 A20 162 RSVD 129 D59_E 293 VID12 260 ADS# 227 A4_E 194 BREQ_E 161 RSVD 128 D59 292 A22_E 259 A17_E 226 A4 193 BREQ 160 AHOLD 127 D9_E 291 A22 258 A17 225 A7_E 192 A11_E 159 INV 126 D9 290 PCHK_E 257 A25_E 224 A7 191 A11 158 CLK 125 D28_E 289 PCHK# 256 A25 223 A8_E 190 A10_E 157 VID2_E2 124 D28 288 A14_E 255 PWT_E 222 A8 189 A10 156 VID22 123 D56_E 287 A14 254 PWT 221 A15_E 188 APCHK_E 155 CACHE_E 122 D56 286 A13_E 253 A12_E 220 A15 187 APCHK# 154 CACHE# 121 D44_E 285 A13 252 A12 219 DC_E 186 SMIACT_E 153 MIO_E 120 D44 284 A24_E 251 A9_E 218 D/C# 185 SMIACT# 152 M/IO# 119 D11_E 283 A24 250 A9 217 A16_E 184 RSVD 151 FERR_E 118 D11 282 RESET 249 A26_E 216 A16 183 A5_E 150 FERR# 117 DP3_E 281 A18_E 248 A26 215 A19_E 182 A5 149 D0_E 116 DP3 280 A18 247 A30_E 214 A19 181 INTR 148 D0 115 D39_E 279 A21_E 246 A30 213 SCYC_E 180 NMI 147 D1_E 114 D39 278 A21 245 VID0_E2 212 SCYC 179 INIT 146 D1 113 DP6_E 277 PCD_E 244 VID02 211 ADSC_E 178 HOLD 145 D61_E 112 DP6 276 PCD 243 HITM_E 210 ADSC# 177 IGNNE# 144 D61 111 D8_E 275 BE4_E 242 HITM# 209 BE6_E 176 SMI# 143 D62_E 110 D8 274 BE4# 241 A20M# 208 BE6 175 WB/WT# 142 D62 109 D32_E 273 BE7_E 240 FLUSH# 207 BE3_E 174 BF0 141 DP0_E 108 D32 272 BE7# 239 A3_E 206 BE3 173 BOFF# 140 DP0 107 D36_E 271 A23_E 238 A3 205 HLDA_E 172 NA# 139 D21_E 106 D36 270 A23 237 A31_E 204 HLDA 171 BF1 138 D21 105 D51_E 269 LOCK_E 236 A31 203 BE1_E 170 BRDYC# 137 D57_E 104 D51 268 LOCK# 235 A29_E 202 BE1# 169 BRDY# 136 D57 103 D15_E 267 BE0_E 234 A29 201 EADS# 168 STPCLK# 135 D5_E 102 D15 266 BE0# 233 WR_E 200 BE2_E 167 BF2 134 D5 101 D37_E 265 BE5_E 232 W/R# 199 BE2# 166 KEN# 133 D24_E 100 D37 264 BE5# 231 HIT_E 198 AP_E 165 EWBE# 132 D24 99 D41_E Chapter 13 Test and Debug 257

Section	Page
IF YOU HAVE QUESTIONS, WE\	3
Contents	5
List of Figures	9
List of Tables	13
Revision History	17
About this Data Sheet	19
1 AMDK6™2E+ Embedded Processor	23
1.1 AMDK6™2E+ Embedded Processor Features	25
1.2 Process Technology	29
1.3 Super7™ Platform	30
2 Internal Architecture	33
2.1 Microarchitecture Overview	33
2.2 Cache, Instruction Prefetch, and Predecode Bits	38
2.3 Instruction Fetch and Decode	39
2.4 Centralized Scheduler	43
2.5 Execution Units	44
2.6 BranchPrediction Logic	47
3 Software Environment	49
3.1 Registers	49
3.2 ModelSpecific Registers (MSR)	66
3.3 Memory Management Registers	76
3.4 Paging	78
3.5 Descriptors and Gates	81
3.6 Exceptions and Interrupts	84
3.7 Instructions Supported by the AMDK6™2E+ Processor	85
4 Logic Symbol Diagram	113
5 Signal Descriptions	115
5.1 Signal Terminology	115
5.2 A20M# (Address Bit 20 Mask)	116
5.3 A[31:3] (Address Bus)	117
5.4 ADS# (Address Strobe)	118
5.5 ADSC# (Address Strobe Copy)	118
5.6 AHOLD (Address Hold)	119
5.7 AP (Address Parity)	120
5.8 APCHK# (Address Parity Check)	121
5.9 BE[7:0]# (Byte Enables)	122
5.10 BF[2:0] (Bus Frequency)	123
5.11 BOFF# (Backoff)	124
5.12 BRDY# (Burst Ready)	125
5.13 BRDYC# (Burst Ready Copy)	126
5.14 BREQ (Bus Request)	126
5.15 CACHE# (Cacheable Access)	127
5.16 CLK (Clock)	127
5.17 D/C# (Data/Code)	128
5.18 D[63:0] (Data Bus)	129
5.19 DP[7:0] (Data Parity)	130
5.20 EADS# (External Address Strobe)	131
5.21 EWBE# (External Write Buffer Empty)	132
5.22 FERR# (FloatingPoint Error)	133
5.23 FLUSH# (Cache Flush)	134
5.24 HIT# (Inquire Cycle Hit)	135
5.25 HITM# (Inquire Cycle Hit To Modified Line)	135
5.26 HLDA (Hold Acknowledge)	136
5.27 HOLD (Bus Hold Request)	137
5.28 IGNNE# (Ignore Numeric Exception)	138
5.29 INIT (Initialization)	139
5.30 INTR (Maskable Interrupt)	140
5.31 INV (Invalidation Request)	140
5.32 KEN# (Cache Enable)	141
5.33 LOCK# (Bus Lock)	142
5.34 M/IO# (Memory or I/O)	143
5.35 NA# (Next Address)	144
5.36 NMI (NonMaskable Interrupt)	145
5.37 PCD (Page Cache Disable)	146
5.38 PCHK# (Parity Check)	147
5.39 PWT (Page Writethrough)	148
5.40 RESET (Reset)	149
5.41 RSVD (Reserved)	150
5.42 SCYC (Split Cycle)	151
5.43 SMI# (System Management Interrupt)	152
5.44 SMIACT# (System Management Interrupt Active)	153
5.45 STPCLK# (Stop Clock)	154
5.46 TCK (Test Clock)	155
5.47 TDI (Test Data Input)	155
5.48 TDO (Test Data Output)	155
5.49 TMS (Test Mode Select)	156
5.50 TRST# (Test Reset)	156
5.51 VCC2DET (VCC2 Detect)	157
5.52 VCC2H/L# (VCC2 High/Low)	158
5.53 VID[4:0] (Voltage Identification)	159
5.54 W/R# (Write/Read)	160
5.55 WB/WT# (Writeback or Writethrough)	161
5.56 Pin Tables by Type	162
5.57 Bus Cycle Definitions	164
6 AMD PowerNow!™ Technology	165
6.1 Enhanced Power Management Features	165
6.2 Dynamic Core Frequency and Core Voltage Control	172
7 Bus Cycles	175
7.1 Timing Diagrams	175
7.2 Bus States	177
7.3 Memory Reads and Writes	180
7.4 I/O Read and Write	188
7.5 Inquire and Bus Arbitration Cycles	190
7.6 Special Bus Cycles	212
8 Poweron Configuration and Initialization	221
8.1 Signals Sampled During the Falling Transition of RESET	221
8.2 RESET Requirements	222
8.3 State of Processor After RESET	222
8.4 State of Processor After INIT	225
9 Cache Organization	227
9.1 MESI States in the L1 Data Cache and L2 Cache	229
9.2 Predecode Bits	230
9.3 Cache Operation	230
9.4 Cache Disabling and Flushing	233
9.5 L2 Cache Testing	235
9.6 CacheLine Fills	235
9.7 CacheLine Replacements	236
9.8 Write Allocate	237
9.9 Prefetching	242
9.10 Cache States	243
9.11 Cache Coherency	244
9.12 Writethrough and Writeback Coherency States	249
9.13 A20M# Masking of Cache Accesses	249
10 Write Merge Buffer	251
10.1 EWBE# Control	251
10.2 Memory Type Range Registers	253
10.3 Memory-Range Restrictions	255
10.4 Examples	257
11 FloatingPoint and Multimedia Execution Units	259
11.1 FloatingPoint Execution Unit	259
11.2 Multimedia and 3DNow!™ Execution Units	261
11.3 FloatingPoint and MMX™/3DNow!™ Instruction Compatibility	262
12 System Management Mode (SMM)	263
12.1 SMM Operating Mode and Default Register Values	263
12.2 SMM StateSave Area	265
12.3 SMM Revision Identifier	267
12.4 SMM Base Address	268
12.5 Halt Restart Slot	268
12.6 I/O Trap Doubleword	269
12.7 I/O Trap Restart Slot	270
12.8 Exceptions, Interrupts, and Debug in SMM	272
13 Test and Debug	273
13.1 BuiltIn SelfTest (BIST)	273
13.2 ThreeState Test Mode	274
13.3 BoundaryScan Test Access Port (TAP)	275
13.4 Cache Inhibit	285
13.5 L2 Cache and Tag Array Testing	286
13.6 Debug	290
14 Clock Control	297
14.1 Clock Control States	297
14.2 Halt State	300
14.3 Stop Grant State	300
14.4 Stop Grant Inquire State	302
14.5 EPM Stop Grant State	303
14.6 Stop Clock State	305
15 Electrical Data	307
15.1 Operating Ranges	308
15.2 Absolute Ratings	309
15.3 DC Characteristics	309
15.4 Power Dissipation	311
15.5 Power and Grounding	313
16 Signal Switching Characteristics	317
16.1 CLK Switching Characteristics	318
16.2 Clock Switching Characteristics for 100MHz Bus Operation	318
16.3 Clock Switching Characteristics for 66MHz Bus Operation	319
16.4 Valid Delay, Float, Setup, and Hold Timings	320
16.5 Output Delay Timings for 100MHz Bus Operation	320
16.6 Input Setup and Hold Timings for 100MHz Bus Operation	322
16.7 Output Delay Timings for 66MHz Bus Operation	324
16.8 Input Setup and Hold Timings for 66MHz Bus Operation	326
16.9 RESET and Test Signal Timing	328
16.10 Timing Diagrams	331
17 Thermal Design	335
17.1 Package Thermal Specifications	335
17.2 Measuring Case Temperature	339
17.3 Layout and Airflow Considerations	339
18 Pin Designations	343
18.1 Pins Designations for CPGA Package	344
18.2 Pins Designations for OBGA Package	348
19 Package Specifications	353
19.1 321Pin Staggered CPGA Package Specification	353
19.2 349Ball OBGA Package Specification	354
20 Ordering Information	355

Match case Limit results 1 per page

Chapter 13

Test and Debug

257

23542A/0—September 2000

AMD-K6™-2E+ Embedded Processor Data Sheet

Preliminary Information

Table 50.

Boundary Scan Bit Definitions

Bit

Pin/Enable

Bit

Pin/Enable

Bit

Pin/Enable

Bit

Pin/Enable

Bit

Pin/Enable

Bit

Pin/Enable

296

A6_E

263

A28_E

230

HIT#

197

164

RSVD

131

D40_E

295

262

A28

229

A27_E

196

A20_E

163

RSVD

130

D40

294

VID1_E

261

ADS_E

228

A27

195

A20

162

RSVD

129

D59_E

293

VID1

260

ADS#

227

A4_E

194

BREQ_E

161

RSVD

128

D59

292

A22_E

259

A17_E

226

193

BREQ

160

AHOLD

127

D9_E

291

A22

258

A17

225

A7_E

192

A11_E

159

INV

126

290

PCHK_E

257

A25_E

224

191

A11

158

CLK

125

D28_E

289

PCHK#

256

A25

223

A8_E

190

A10_E

157

VID2_E

124

D28

288

A14_E

255

PWT_E

222

189

A10

156

VID2

123

D56_E

287

A14

254

PWT

221

A15_E

188

APCHK_E

155

CACHE_E

122

D56

286

A13_E

253

A12_E

220

A15

187

APCHK#

154

CACHE#

121

D44_E

285

A13

252

A12

219

DC_E

186

SMIACT_E

153

MIO_E

120

D44

284

A24_E

251

A9_E

218

D/C#

185

SMIACT#

152

M/IO#

119

D11_E

283

A24

250

217

A16_E

184

RSVD

151

FERR_E

118

D11

282

RESET

249

A26_E

216

A16

183

A5_E

150

FERR#

117

DP3_E

281

A18_E

248

A26

215

A19_E

182

149

D0_E

116

DP3

280

A18

247

A30_E

214

A19

181

INTR

148

115

D39_E

279

A21_E

246

A30

213

SCYC_E

180

NMI

147

D1_E

114

D39

278

A21

245

VID0_E

212

SCYC

179

INIT

146

113

DP6_E

277

PCD_E

244

VID0

211

ADSC_E

178

HOLD

145

D61_E

112

DP6

276

PCD

243

HITM_E

210

ADSC#

177

IGNNE#

144

D61

111

D8_E

275

BE4_E

242

HITM#

209

BE6_E

176

SMI#

143

D62_E

110

274

BE4#

241

A20M#

208

BE6

175

WB/WT#

142

D62

109

D32_E

273

BE7_E

240

FLUSH#

207

BE3_E

174

BF0

141

DP0_E

108

D32

272

BE7#

239

A3_E

206

BE3

173

BOFF#

140

DP0

107

D36_E

271

A23_E

238

205

HLDA_E

172

NA#

139

D21_E

106

D36

270

A23

237

A31_E

204

HLDA

171

BF1

138

D21

105

D51_E

269

LOCK_E

236

A31

203

BE1_E

170

BRDYC#

137

D57_E

104

D51

268

LOCK#

235

A29_E

202

BE1#

169

BRDY#

136

D57

103

D15_E

267

BE0_E

234

A29

201

EADS#

168

STPCLK#

135

D5_E

102

D15

266

BE0#

233

WR_E

200

BE2_E

167

BF2

134

101

D37_E

265

BE5_E

232

W/R#

199

BE2#

166

KEN#

133

D24_E

100

D37

264

BE5#

231

HIT_E

198

AP_E

165

EWBE#

132

D24

D41_E