AMD AMD-K6-2/400 User Guide - Page 213
Basic Special Bus Cycle Halt Cycle, Halt Cycle, A[31:3], BE[7:0]
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BRDY# Table 33). A halt special cycle is generated after the processor executes the HLT instruction. If the processor samples FLUSH# asserted, it writes back any L1 data cache and L2 cache lines that are in the modified state and invalidates all lines in all caches. The processor then drives a flush acknowledge special cycle. If the processor executes a WBINVD instruction, it drives a writeback special cycle after the processor completes invalidating and writing back the cache lines. Halt Cycle A[4:3] = 00b FBh Figure 77. Basic Special Bus Cycle (Halt Cycle) Chapter 7 Bus Cycles 191
Chapter 7
Bus Cycles
191
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
Preliminary Information
Table 33). A halt special cycle is generated after the processor
executes the HLT instruction.
If the processor samples FLUSH# asserted, it writes back any
L1 data cache and L2 cache lines that are in the modified state
and invalidates all lines in all caches. The processor then drives
a flush acknowledge special cycle.
If the processor executes a WBINVD instruction, it drives a
writeback special cycle after the processor completes
invalidating and writing back the cache lines.
Figure 77.
Basic Special Bus Cycle (Halt Cycle)
Halt Cycle
A[4:3] = 00b
FBh
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BRDY#