AMD AMD-K6-2/400 User Guide - Page 297
Clock Control, 14.1 Clock Control States
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 14 Clock Control 14.1 Clock Control States The standard-power versions of the AMD-K6-2E+ processor support five modes of clock control. The low-power versions of the AMD-K6-2E+ processor support six modes of clock control. The processor can transition between these modes to maximize performance, to minimize power dissipation, or to provide a balance between performance and power. (See "Power Dissipation" on page 289 for the maximum power dissipation of t h e A M D -K 6 -2 E + p ro c e s s o r w i t h i n t h e n o r m a l a n d reduced-power states.) The clock-control states supported are: s Normal State-The processor is running in Real Mode, Virtual-8086 Mode, Protected Mode, or System Management Mode (SMM). In this state, all clocks are running-including the external bus clock CLK and the internal processor clock-and the full features and functions of the processor are available. s Halt State-This low-power state is entered following the successful execution of the HLT instruction. During this state, the internal processor clock is stopped. s Stop Grant State-This low-power state is entered following the recognition of the assertion of the STPCLK# signal. During this state, the internal processor clock is stopped. s Stop Grant Inquire State-This state is entered from the Halt state and the Stop Grant state as the result of a system-initiated inquire cycle. s Enhanced Power Management (EPM) Stop Grant State: This low-power state is available on low--power versions of the processor. It is entered following the write of a non-zero value to the SGTC field of the EPM 16-byte I/O block for the purpose of performing dynamic processor core frequency and voltage ID state transitions using AMD PowerNow! technology. During this state, the internal processor clock is stopped. s Stop Clock State-This low-power state is entered from the Stop Grant state when the CLK signal is stopped. Chapter 14 Clock Control 275