AMD AMD-K6-2/400 User Guide - Page 164
Bus Cycle Definitions
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.57 Bus Cycle Definitions Table 23. Bus Cycle Definition Bus Cycle Initiated Code Read, L1 Instruction Cache and L2 Cache Line Fill Code Read, Noncacheable Code Read, Noncacheable Encoding for Special Cycle Interrupt Acknowledge I/O Read I/O Write Memory Read, L1 Data Cache and L2 Cache Line Fill Memory Read, Noncacheable Memory Read, Noncacheable Memory Write, L1 Data Cache or L2 Cache Writeback Memory Write, Noncacheable Notes: 1. x means "don't care" Generated by the CPU Generated by System Logic M/IO# 1 1 1 0 0 0 0 1 1 1 1 1 D/C# 0 0 0 0 0 1 1 1 1 1 1 1 W/R# 0 0 0 1 0 0 1 0 0 0 1 1 CACHE# 0 1 x 1 1 1 1 0 1 x 0 1 KEN# 0 x1 1 x x x x 0 x 1 x x Table 24. Special Cycles Special Cycle Stop Grant Enhanced Power Management (EPM) Stop Grant2 Flush Acknowledge (FLUSH# sampled asserted) Writeback (WBINVD instruction) Halt Flush (INVD, WBINVD instruction) Shutdown 1 1 1 1 1 1 0 1 1 0 0 1 1 x1 0101111110011x 0111011110011x 0111101110011x 0111110110011x 0111111010011x 0111111100011x Notes: 1. x means "don't care". 2. Supported on the low-power versions only. A4 BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# M/IO# D/C# W/R# CACHE# KEN# 142 Signal Descriptions Chapter 5