AMD AMD-K6-2/400 User Guide - Page 298
Clock Control,
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Figure 101 and Figure 102 illustrate the clock control state transitions on the standard-power and low-power versions, respectively, of the AMD-K6-2E+ processor. Each of the reduced-power states are described in the following sections. HLT Instruction RESET, SMI#, INIT, or INTR Asserted Normal Mode - Real - Virtual-8086 - Protected - SMM STPCLK# Asserted STPCLK# Negated, or RESET Asserted Halt State EADS# Asserted Writeback Completed Stop Grant Inquire State EADS# Asserted Writeback Completed Stop Grant State CLK Started CLK Stopped Stop Clock State Figure 101. Clock Control State Transitions for Standard-Power Versions of the AMD-K6™-2E+ Processor 276 Clock Control Chapter 14