AMD AMD-K6-2/400 User Guide - Page 232
Cache Organization, Table 36., PWT Signal Generation
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 36 describes how the PWT signal is driven based on the values of the PWT bits and the PG bit of CR0. Table 36. PWT Signal Generation PWT Bit1 1 0 1 0 PG Bit of CR0 1 1 0 0 Notes: 1. PWT is taken from PTE or PDE. PWT Signal High Low Low Low Table 37 describes how the PCD signal is driven based on the values of the CD bit of CR0, the PCD bits, and the PG bit of CR0. Table 37. PCD Signal Generation CD Bit of CR0 1 0 0 0 0 PCD Bit1 X 1 0 1 0 Notes: 1. PCD is taken from PTE or PDE. PG Bit of CR0 X 1 1 0 0 PCD Signal High High Low Low Low Table 38 describes how the CACHE# signal is driven based on the cycle type, the CI bit of TR12, the PCD signal, and the UWCCR model-specific register. 210 Cache Organization Chapter 9