AMD AMD-K6-2/400 User Guide - Page 320
Valid Delay, Float, Setup, and Hold Timings, 16.5 Output Delay Timings for 100MHz Bus Operation
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.4 Valid Delay, Float, Setup, and Hold Timings Valid Delay and Float Timing The maximum valid delay timings are provided to allow a system designer to determine if setup times to the system logic can be met. Likewise, the minimum valid delay timings are used to analyze hold times to the system logic. s Valid delay and float timings are given for output signals during functional operation and are given relative to the rising edge of CLK. s During boundary-scan testing, valid delay and float timings for output signals are with respect to the falling edge of TCK. Setup and Hold Timing The setup and hold time requirements for the AMD-K6-2E+ processor input signals must be met by the system logic to assure the proper operation of the AMD-K6-2E+ processor. s The setup and hold timings during functional and boundary-scan test mode are given relative to the rising edge of CLK and TCK, respectively. 16.5 Output Delay Timings for 100-MHz Bus Operation Table 64. Output Delay Timings for 100-MHz Bus Operation Symbol Parameter Description t6 A[31:3] Valid Delay t7 A[31:3] Float Delay t8 ADS# Valid Delay t9 ADS# Float Delay t10 ADSC# Valid Delay t11 ADSC# Float Delay t12 AP Valid Delay t13 AP Float Delay t14 APCHK# Valid Delay t15 BE[7:0]# Valid Delay t16 BE[7:0]# Float Delay t17 BREQ Valid Delay t18 CACHE# Valid Delay Preliminary Data Min 1.1 ns 1.0 ns 1.0 ns 1.0 ns 1.0 ns 1.0 ns 1.0 ns 1.0 ns Max 4.0 ns 7.0 ns 4.0 ns 7.0 ns 4.0 ns 7.0 ns 5.5 ns 7.0 ns 4.5 ns 4.0 ns 7.0 ns 4.0 ns 4.0 ns Figure 106 107 106 107 106 107 106 107 106 106 107 106 106 298 Signal Switching Characteristics Chapter 16