AMD AMD-K6-2/400 User Guide - Page 314
Decoupling, Recommendations, Suggested Component Placement for CPGA Package
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 0.254mm (min.) for isolation region C14 CC10 C8 CC9 C15 C9 CC8 C5 C18 C17 C20 C6 C19 C21 C7 + C1 + CC3 C22 C23 + CC4 C24 C11 C2 + + CC5 C25 CC6 C29 C12 C27 C30 C13 C26 C28 C31 C16 CC7 C10 Decoupling Recommendations VCC3 (I/O) Plane VCC2 (Core) Plane CC1 CC2 Figure 103. Suggested Component Placement for CPGA Package In addition to the isolation region mentioned in "Power Connections" on page 291, adequate decoupling capacitance is required between the two system power planes and the ground plane to minimize ringing and to provide a low-impedance path for return currents. Suggested decoupling capacitor placement is shown in Figure 103. Surface-mounted capacitors should be used under the processor's ZIF socket to minimize resistance and inductance in the lead lengths while maintaining minimal height. For information and recommendations about the specific value, quantity, and location of the capacitors, see the AMD-K6® Processor Power Supply Design Application Note, order# 21103. 292 Electrical Data Chapter 15