AMD AMD-K6-2/400 User Guide - Page 361

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Hold acknowledge cycle 168 acknowledge signal 114, 168-170 HOLD Signal 115 -initiated inquire hit to modified line 172 -initiated inquire hit to shared or exclusive line 170 timing 295, 310 I I/O misaligned read and write 167 read and write 166 trap doubleword 247 trap restart slot 248 IBF Field 147 IDCODE Instruction 260 IEEE 1149.1 2, 253 IEEE 754 2, 31, 237 IEEE 854 237 IGNNE# Signal 116, 238, 240 Ignore Numeric Exception 116 INIT Signal 117, 242, 278 -initiated transition from protected mode to real mode 196 processor state after 203 Initialization 117 output signal state 200 power-on configuration 199 processor state after INIT 203 processor state after RESET 200 register state 200 RESET requirements 200 signals sampled during RESET 199 Input capacitance 288 leakage current 288 pin float conditions (table 141 pin types (table 140 setup and hold timing 100-MHz bus operation 300 66-MHz bus operation 304 Input/Output (I/O) capacitance 288 Inquire 171, 173, 175, 275 bus arbitration cycles 168 cycle hit 113 cycle hit to modified line 113 cycles 94-99, 109, 113-114, 131, 139, 164, 168 170, 172, 174, 176-178, 180, 182, 186, 222 263, 275, 278-280 miss, AHOLD-initiated 174 Instructions 63 3DNow!™ technology 89-90, 239 3DNow!™ technology (table 89-90 cache 16 decode 18 digital signal processing 239 digital signal processing (table 90 EMMS 21 FEMMS 21 fetch 17 floating-point (table 82 integer (table 65 INVD 224 MMX technology 86, 239 MMX technology (table 86 pointer 31 PREFETCH 17, 220 RSM 241 serializing 94 supported by the processor (table 63 Test Access Port (TAP 259 WBINVD 224 Integer data registers 29 data types 29 instructions (table 65 Interrupts 130, 188, 192, 196, 237-238, 240, 242 250, 273, 280 01h 274 03h 274 10h 237 acknowledge 95, 103, 106, 118, 120, 125, 184, 188 acknowledge cycle definition (table 188 acknowledge cycles 95, 98, 100, 106, 123, 138 clock grant state 280 descriptor table register 54 flag 38, 118, 130 floating-point exceptions 237-238 gate 61 INIT 196, 242 INTR 118 IRQ13 239 MMX instructions 240 NMI 123, 203, 242 redirection bitmap 55 request 118 service routine 118, 123, 238, 241 STPCLK 193 summary (table 62 system management 241 type of 62 INTR Signal 118, 278 INV Signal 118 Invalidation Request 118 INVD Instruction 224 IOBASE Field 145 K KEN# Signal 119 L L1 Cache 46 cache line (figure 207 cache-line replacements 214 coherency 222, 227 data cache line (figure 207 disabling 46, 211-212 flushing 223 inquire cycles (table 225 instruction cache line (figure 207 internal snooping 223 MESI states 207 organization 205 organization (figure 206 prefetching 220 sector organization (figure 16 Index 339