AMD AMD-K6-2/400 User Guide - Page 84
Exceptions and Interrupts, Gate Descriptor, Table 11.
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Reserved Symbol P DPL DT Type Description Present/Valid Bit Descriptor Privilege Level Descriptor Type See Table 10 on page 61 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bits 15 14-13 12 11-8 Offset 31-16 P DPL 0 Type Segment Selector Offset 15-0 Figure 53. Gate Descriptor 3.6 Exceptions and Interrupts Table 11 summarizes the exceptions and interrupts. Table 11. Summary of Exceptions and Interrupts Interrupt Number Interrupt Type 0 Divide by Zero Error 1 Debug 2 Non-Maskable Interrupt 3 Breakpoint 4 Overflow 5 Bounds Check 6 Invalid Opcode 7 Device Not Available 8 Double Fault 9 Reserved - Interrupt 13 10 Invalid TSS 11 Segment Not Present 12 Stack Segment 13 General Protection 14 Page Fault 16 Floating-Point Error 17 Alignment Check 0-255 Software Interrupt Cause DIV, IDIV Debug trap or fault NMI signal sampled asserted Int 3 INTO BOUND Invalid instruction ESC and WAIT Fault occurs while handling a fault - Task switch to an invalid segment Instruction loads a segment and present bit is 0 (invalid segment) Stack operation causes limit violation or present bit is 0 Segment related or miscellaneous invalid actions Page protection violation or a reference to missing page Arithmetic error generated by floating-point instruction Data reference to an unaligned operand. (The AC flag and the AM bit of CR0 are set to 1.) INT n 62 Software Environment Chapter 3