AMD AMD-K6-2/400 User Guide - Page 37

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Branch Logic 3DNow!™ Technology s An analogous set of 21 registers is available specifically for MMX and 3DNow! operations. • Twelve of these are MMX/3DNow! rename registers. s Nine are MMX/3DNow! committed or architectural registers, consisting of one scratch register and eight registers that correspond to the MMX registers (mm0-mm7, as shown in Figure 17 on page 35. Th e A M D -K 6 -2 E + p ro c e s s o r i s d e s i g n e d w i t h h i g h ly sophisticated dynamic branch logic consisting of the following: s Branch history/prediction table s Branch target cache s Return address stack The AMD-K6-2E+ processor implements a two-level branch prediction scheme based on an 8192-entry branch history table. The branch history table stores prediction information that is used for predicting conditional branches. Because the branch history table does not store predicted target addresses, special address ALUs calculate target addresses on the fly during instruction decode. The branch target cache augments predicted branch performance by avoiding a one clock cache-fetch penalty. This specialized target cache does this by supplying the first 16 bytes of target instructions to the decoders when branches are predicted. The return address stack is a unique device specifically designed for optimizing CALL and RETURN pairs. In summary, the AMD-K6-2E+ processor uses dynamic branch logic to minimize delays due to the branch instructions that are common in x86 software. AMD has taken a lead role in improving the multimedia and 3D capabilities of the x86 processor family with the introduction of 3DNow! technology, which uses a packed, single-precision, floating-point data format and Single Instruction Multiple Data (SIMD) operations based on the MMX technology model. Chapter 2 Internal Architecture 15