AMD AMD-K6-2/400 User Guide - Page 71
UC/WC Cacheability Control Register UWCCR, Processor State Observability Register PSOR - base frequency
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet UC/WC Cacheability Control Register (UWCCR) . The AMD-K6-2E+ processor provides two variable-range Memory Type Range Registers (MTRRs)-MTRR0 and MTRR1-that each specify a range of memory. Each range can be defined as uncacheable (UC) or write-combining (WC) memory. For more information, see "Memory Type Range Registers" on page 231. The UWCCR register is MSR C000_0085h. Symbol Description Bits UC1 Uncacheable Memory Type 32 WC1 Write-Combining Memory Type 33 Symbol Description Bits UC0 Uncacheable Memory Type 0 WC0 Write-Combining Memory Type 1 63 49 48 34 33 32 31 17 16 2 10 Physical Base Address 1 WU Physical Address Mask 1 C C 11 Physical Base Address 0 WU Physical Address Mask 0 C C 00 MTRR1 MTRR0 Figure 37. UC/WC Cacheability Control Register (UWCCR) Processor State Observability Register (PSOR) . 63 The AMD-K6-2E+ processor provides the Processor State Observability Register (PSOR). The PSOR is defined as shown in Figure 38 for all standard-power versions of the AMD-K6-2E+ processor. For a description of the PSOR register supported by the low-power versions of the processor, see page 148. The PSOR register is MSR C000_0087h. 9 87 432 0 N O L STEP BF 2 Reserved Symbol Description Bit NOL2 No L2 Functionality 8 STEP Processor Stepping 7-4 BF Bus Frequency Divisor 2-0 Figure 38. Processor State Observability Register (PSOR) Chapter 3 Software Environment 49