AMD AMD-K6-2/400 User Guide - Page 73

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Symbol Description T/D Selects Tag (1) or Data (0) access Way Selects desired cache way Bit 20 17-16 31 21 20 19 18 17 16 15 14 T / Way D Reserved Symbol Description Bit Set Selects the desired cache set 14-6 Line Selects Line1 (1) or Line0 (0) 5 Octet Selects one of four octets 4-3 Dword Selects upper (1) or lower (0) dword 2 6 5 4 32 1 0 L D Set i n e Octet w o r d Figure 40. L2 Tag or Data Location for AMD-K6™-2E+ Processor-EDX If the L2 cache data is read (as opposed to reading the tag information), the result (doubleword) is placed in EAX in the format as illustrated in Figure 41. Similarly, if the L2 cache data is written, the write data is taken from EAX. 31 0 Data Figure 41. L2 Data -EAX If the L2 tag is read (as opposed to reading the cache data), the result is placed in EAX in the format as illustrated in Figure 42 on page 52. Similarly, if the L2 tag is written, the write data is taken from EAX. Chapter 3 Software Environment 51