AMD AMD-K6-2/400 User Guide - Page 248
Table 41., L1 and L2 Cache States for Snoops, Flushes, and Invalidation
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 41 shows all possible cache-line states before and after various cache-related operations. Table 41. L1 and L2 Cache States for Snoops, Flushes, and Invalidation Operation Type Internal Snoop FLUSH# Signal PFIR (F/I = 0) PFIR (F/I = 1) WBINVD Instruction INVD Instruction Cache State Before Operation1 L1 L2 I M I E I S I I E3 M3 E E E I M E M I S S S I S or E M - - M S or E M - - M - - S or E M - - M - - Access Type2 Writeback L1 to L2 Writeback L1 to bus - - - Writeback L1 to bus Writeback L2 to bus - Writeback L1 to bus Writeback L2 to bus - - Writeback L1 to bus Writeback L2 to bus - Cache State After Operation L1 L2 I M I E I S I I I M I E I I I M I I I S I I I I I I I I I I I I I I I I I I I I I I I I Notes: 1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and are treated as "valid" states. 2. Writeback cycles to the bus are 32-byte burst writes. 3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in the modified state in the L2 cache. - Not applicable or none. 226 Cache Organization Chapter 9