AMD AMD-K6-2/400 User Guide - Page 222
RESET Requirements, 8.3 State of Processor After RESET, Output Signals, Registers
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 8.2 RESET Requirements During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification. (See "CLK Switching Characteristics" on page 296 for clock specifications. "Electrical Data" beginning on page 285 for VCC specifications.) During a warm reset while CLK and VCC are within specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 8.3 State of Processor After RESET Output Signals Table 34 shows the state of all processor outputs and bidirectional signals immediately after RESET is sampled asserted. Table 34. Output Signal State After RESET Signal A[31:3], AP ADS#, ADSC# APCHK# BE[7:0]# BREQ CACHE# D/C# D[63:0], DP[7:0] FERR# HIT# State Floating High High Floating Low High Low Floating High High HITM# High HLDA Low Notes: 1. Supported on low-power versions only. Signal LOCK# M/IO# PCD PCHK# PWT SCYC SMIACT# TDO VCC2DET VCC2H/L# VID[4:0]1 W/R# State High Low Low High Low Low High Floating Low Low 01010b Low Registers Table 35 on page 201 shows the state of all architecture registers and Model-Specific Registers (MSRs) after the processor has completed its initialization due to the recognition of the assertion of RESET. 200 Power-on Configuration and Initialization Chapter 8