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POST Error Messages and Handling

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Intel® Server Board X38ML Error Reporting and Handling Checkpoint 0x34h 0x35h 0x3Fh Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB OFF G R R OFF G R A G G A A Description Loading crisis recovery capsule Handing off control to the crisis recovery capsule Unable to complete crisis recovery 6.3.3 POST Error Messages and Handling Whenever possible, the BIOS outputs the boot progress codes to the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity. Based on the data bit availability to display progress codes, a progress code can be customized to fit the data width. The higher the data bit, the higher the granularity of information that can be sent on the progress port. The progress codes may be reported by the system BIOS or option ROMs. The Response section in the following table is divided into three types: ƒ Minor: The message displays on the screen or in the Error Manager screen. The system continues booting with a degraded state. The user may want to replace the erroneous unit. The setup POST error Pause setting does not have any effect with this error. ƒ Major: The message displays in the Error Manager screen, and an error is logged to the SEL. The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error, where the user can take immediate corrective action or choose to continue booting. ƒ Fatal: The message displays in the Error Manager screen, an error is logged to the SEL, and the system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system. The setup POST error Pause setting does not have any effect with this error. Table 50. POST Error Messages and Handling Error Code 0012 0048 0108 0109 0140 0141 0146 0198 5220 5221 5224 8110 8120 8140 CMOS date/time not set Error Message Password check failed Keyboard component encountered a locked error. Keyboard component encountered a stuck key error. PCI component encountered a PERR error. PCI resource conflict Insufficient memory to shadow PCI ROM Processor family is unsupported CMOS/NVRAM Configuration Cleared Passwords cleared by jumper Password clear Jumper is Set. Processor 01 internal error (IERR) on last boot Processor 01 thermal trip error on last boot Processor 01 Failed FRB-3 Timer Response Major Fatal Minor Minor Major Major Major Major Major Major Major Major Major Minor Revision 1.3 101 Intel order number E15331-006

Section	Page
1. Introduction	13
1.1 Server Board Use Disclaimer	13
2. Server Board Overview	14
2.1 Server Board Feature Set	14
2.2 Server Board Layout	16
3. Functional Architecture	19
3.1 Processor Subsystem	20
3.2 Intel® X38 Chipset	20
3.2.2.1 Direct Media Interface (DMI)	21
3.2.2.2 PCI Express* Interfaces	21
3.2.2.3 Serial ATA II Interface	22
3.2.2.4 Low Pin Count Interface (LPC)	22
3.2.2.5 Compatibility Modules	22
3.2.2.6 Universal Serial Bus (USB) Controller	22
3.2.2.7 Real Time Clock (RTC)	23
3.2.2.8 GPIO	23
3.2.2.9 Enhanced Power Management	23
3.2.2.10 System Management Interface	23
3.2.2.11 Serial Peripheral Interface (SPI)	23
3.2.2.12 Manageability	24
3.3 Integrated Baseboard Management Controller	24
3.4 Memory Subsystem	27
3.5 I/O Subsystem	28
3.5.2.1 SATA RAID	28
3.5.2.2 Intel® RAID Technology Option ROM	29
3.5.6.1 Serial Ports	30
3.5.6.2 Keyboard and Mouse Support	31
3.5.6.3 Wake-up Control	31
3.6 Replacing the Back-Up Battery	31
4. System BIOS	33
4.1 BIOS Identification String	33
4.2 Logo/Diagnostic Screen	33
4.3 BIOS Setup Utility	34
4.3.1.1 Setup Page Layout	34
4.3.1.2 Entering BIOS Setup	35
4.3.1.3 Keyboard Commands	35
4.3.1.4 Menu Selection Bar	36
4.3.2.1 Main Screen	37
4.3.2.2 Advanced Screen	39
4.3.2.2.1 Processor Configuration Screen	40
4.3.2.2.2 Memory Configuration Screen	42
4.3.2.2.3 SATA Controller Configuration Screen	44
4.3.2.2.4 Serial Ports Screen	45
4.3.2.2.5 USB Configuration Screen	46
4.3.2.2.6 PCI Screen	48
4.3.2.3 Security Screen	49
4.3.2.4 Server Management Screen	51
4.3.2.4.1 Console Redirection Screen	52
4.3.2.4.2 System Information Screen	54
4.3.2.5 Boot Options Screen	55
4.3.2.5.1 Hard Disk Order Screen	56
4.3.2.5.2 CDROM Order Screen	56
4.3.2.5.3 Floppy Order Screen	57
4.3.2.5.4 Network Device Order Screen	58
4.3.2.5.5 BEV Device Order Screen	58
4.3.2.6 Boot Manager	59
4.3.2.7 Error Manager Screen	60
4.3.2.8 Exit Screen	60
4.4 Loading BIOS Defaults	62
4.5 Multiple Boot Blocks	62
4.6 Recovery Mode	63
4.7 OEM Logo	63
5. Platform Management	65
5.1 Platform Management Features	65
5.2 Power System	66
5.2.5.1 Power Button Signal	68
5.2.5.2 Chipset Sleep S4/S5	69
5.2.5.3 Power-On Enable	69
5.2.5.4 Power-down Disable	69
5.3 Advanced Configuration and Power Interface (ACPI)	70
5.4 System Reset Control	71
5.5 BMC Reset Control	72
5.6 System Initialization	72
5.6.2.1 Watchdog Timer Timeout Reason Bits	73
5.7 Integrated Front Panel User Interface	74
5.7.3.1 Chassis Intrusion	75
5.7.3.2 Power Button	75
5.7.3.3 Reset Button	75
5.8 Private Management I2C Buses	76
5.9 Watchdog Timer	76
5.10 BMC Internal Timestamp Clock	76
5.11 System Event Log (SEL)	77
5.12 Sensor Data Record (SDR) Repository	77
5.13 Field Replaceable Unit (FRU) Inventory Device	78
5.14 Sensor Rearm Behavior	79
5.15 Processor Sensors	80
5.15.1.1 ThermTrip Monitoring	80
5.15.1.2 IERR Monitoring	81
5.15.2.1 PECI Interface	81
5.16 Standard Fan Management	81
5.17 Power Unit Management	83
5.18 BMC Self Test	84
5.19 Messaging Interfaces	84
5.19.6.1 LPC/KCS Interface	85
5.19.6.2 Receive Message Queue	86
5.19.6.3 SMS/SMM Status Register	86
5.19.6.4 Server Management Software (SMS) Interface	86
5.19.6.5 SMM Interface	87
5.19.8.1 Serial-over-LAN (SOL 2.0)	88
5.20 Event Filtering and Alerting	88
5.21 Sensor Support	89
5.22 BIOS-BMC interactions	95
5.23 Platform Management Features Implemented by BIOS	95
5.23.2.1 Serial Configuration Settings	96
5.23.2.2 Keystroke Mappings	96
5.23.2.2.1 Standalone <Esc> Key for Headless Operation	96
5.23.2.3 Limitations	97
5.23.2.4 Interface to Server Management	97
5.23.3.1 Channel Access Modes	97
5.23.3.2 Interaction with BIOS Console Redirection	97
5.23.3.3 SOL, EMP and Console Redirection Use Case Model	98
5.23.4.1 PXE BIOS Support	100
5.23.6.1 Password Clear Jumper	101
6. Error Reporting and Handling	102
6.1 Fault Resilient Booting	102
6.2 Error Handling and Logging	103
6.2.2.1 PCI Bus Error	103
6.2.2.2 PCI Express* Errors	103
6.2.2.3 Processor Bus Error	104
6.2.2.4 Memory Bus Error	104
6.2.2.5 Operating System Watchdog Failure	104
6.2.2.6 Boot Event	104
6.2.3.1 Memory Error Events	105
6.2.3.2 Examples of Event Data Field Contents for Memory Errors	106
6.2.3.3 PCI Error Events	106
6.2.3.4 Examples of Event Data Field Contents for PCI Errors	107
6.2.3.5 FRB-2 Error Events	107
6.2.4.1 No Real-Time Clock (RTC) Access	108
6.3 Error Messages and Error Codes	109
7. Connectors and Jumper Blocks	116
7.1 Power Connectors	116
7.2 PCI Express* x16 Connector	116
7.3 SMBus Connector	118
7.4 Front Panel Connector	118
7.5 I/O Connectors	119
7.6 Fan Headers	122
7.7 Chassis Intrusion Header	122
7.8 Jumper Blocks	123
8. Design and Environmental Specifications	124
8.1 Server Board Design Specification	124
8.2 Product Regulatory Compliance	124
8.3 Electromagnetic Compatibility Notices	127
Glossary	128

Match case Limit results 1 per page

Intel® Server Board X38ML

Error Reporting and Handling

Revision 1.3

Intel order number E15331-006

101

Diagnostic LED Decoder

G=Green, R=Red, A=Amber

Checkpoint

MSB

LSB

Description

0x34h

OFF

Loading crisis recovery capsule

0x35h

OFF

Handing off control to the crisis recovery capsule

0x3Fh

Unable to complete crisis recovery

6.3.3

POST Error Messages and Handling

Whenever possible, the BIOS outputs the boot progress codes to the video screen. Progress

codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and

operation information. The class and subclass fields point to the type of hardware being

initialized. The operation field represents the specific initialization activity. Based on the data bit

availability to display progress codes, a progress code can be customized to fit the data width.

The higher the data bit, the higher the granularity of information that can be sent on the

progress port. The progress codes may be reported by the system BIOS or option ROMs.

The Response section in the following table is divided into three types:

Minor:

The message displays on the screen or in the Error Manager screen. The system

continues booting with a degraded state. The user may want to replace the erroneous

unit. The setup POST error Pause setting does not have any effect with this error.

Major:

The message displays in the Error Manager screen, and an error is logged to the

SEL. The setup POST error Pause setting determines whether the system pauses to the

Error Manager for this type of error, where the user can take immediate corrective action

or choose to continue booting.

Fatal:

The message displays in the Error Manager screen, an error is logged to the SEL,

and the system cannot boot unless the error is resolved. The user needs to replace the

faulty part and restart the system. The setup POST error Pause setting does not have

any effect with this error.

Table 50. POST Error Messages and Handling

Error Code

Error Message

Response

0012

CMOS date/time not set

Major

0048

Password check failed

Fatal

0108

Keyboard component encountered a locked error.

Minor

0109

Keyboard component encountered a stuck key error.

Minor

0140

PCI component encountered a PERR error.

Major

0141

PCI resource conflict

Major

0146

Insufficient memory to shadow PCI ROM

Major

0198

Processor family is unsupported

Major

5220

CMOS/NVRAM Configuration Cleared

Major

5221

Passwords cleared by jumper

Major

5224

Password clear Jumper is Set.

Major

8110

Processor 01 internal error (IERR) on last boot

Major

8120

Processor 01 thermal trip error on last boot

Major

8140

Processor 01 Failed FRB-3 Timer

Minor