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Intel X38ML Product Specification - Page 76

Private Management I, C Buses, Watchdog Timer, BMC Internal Timestamp Clock

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Platform Management Intel® Server Board X38ML 5.8 Private Management I2C Buses The BMC controls multiple private I2C buses. The BMC is the sole master on these buses. External agents must use the BMC's Master Write/Read I2C command if they require direct communication with a device on any of these buses. Only FRU devices are accessible in this manner. Sensor devices should not be directly accessed by BMC clients. 5.9 Watchdog Timer The BMC implements a fully IPMI 2.0-compatible watchdog timer. See the IPMI 2.0 specification. A watchdog pre-timeout interrupt signal assertion is not supported. 5.10 BMC Internal Timestamp Clock The BMC maintains a 4-byte internal timestamp clock that subsystems, such as the SEL, use. The timestamp value is derived from an RTC element internal to the BMC. This internal timestamp clock is read and set using the Get SEL Time and Set SEL Time commands, respectively. You can also use the Get SDR Time command to read the timestamp clock. The IPMI 2.0 specification specifies the commands and the IPMI time format. 5.10.1 BMC Clock Initialization During system initialization the BMC cannot guarantee the validity of its internal timestamp, so it resets its clock counter to zero. The BMC attempts to retrieve the current time from an internal battery-backed RTC element. If the RTC time is in the pre-init range of 0 to 0x20000000, then the BMC ignores it and continues counting from zero, and any SEL events have pre-init timestamps relative to the approximate time of the BMC initialization. Whenever the BMC receives the Set SEL Time command, it updates the integrated RTC value. This helps ensure the BMC internal clock maintains synchronization with the system clock across BMC initializations. Using the Set SEL Time command to force the BMC to a pre-init timestamp causes the RTC to be updated with the same value. Unless the Set SEL Time command is sent with a valid time before the next BMC initialization, the BMC ignores the preinit time stored in the RTC. 5.10.2 System Clock Synchronization The BMC does not have direct access to the system clock used by BIOS and the operating system. The BIOS must send the Set SEL Time command with the current system time to the BMC during the system Power-on Self-Test (POST). Synchronization during very early POST is preferred, so any SEL entries recorded during system boot have an accurate time stamp. If the time is modified through an operating system interface, then the BMC's time is not synchronized until the next system reboot. 64 Revision 1.3 Intel order number E15331-006

Section	Page
1. Introduction	13
1.1 Server Board Use Disclaimer	13
2. Server Board Overview	14
2.1 Server Board Feature Set	14
2.2 Server Board Layout	16
3. Functional Architecture	19
3.1 Processor Subsystem	20
3.2 Intel® X38 Chipset	20
3.2.2.1 Direct Media Interface (DMI)	21
3.2.2.2 PCI Express* Interfaces	21
3.2.2.3 Serial ATA II Interface	22
3.2.2.4 Low Pin Count Interface (LPC)	22
3.2.2.5 Compatibility Modules	22
3.2.2.6 Universal Serial Bus (USB) Controller	22
3.2.2.7 Real Time Clock (RTC)	23
3.2.2.8 GPIO	23
3.2.2.9 Enhanced Power Management	23
3.2.2.10 System Management Interface	23
3.2.2.11 Serial Peripheral Interface (SPI)	23
3.2.2.12 Manageability	24
3.3 Integrated Baseboard Management Controller	24
3.4 Memory Subsystem	27
3.5 I/O Subsystem	28
3.5.2.1 SATA RAID	28
3.5.2.2 Intel® RAID Technology Option ROM	29
3.5.6.1 Serial Ports	30
3.5.6.2 Keyboard and Mouse Support	31
3.5.6.3 Wake-up Control	31
3.6 Replacing the Back-Up Battery	31
4. System BIOS	33
4.1 BIOS Identification String	33
4.2 Logo/Diagnostic Screen	33
4.3 BIOS Setup Utility	34
4.3.1.1 Setup Page Layout	34
4.3.1.2 Entering BIOS Setup	35
4.3.1.3 Keyboard Commands	35
4.3.1.4 Menu Selection Bar	36
4.3.2.1 Main Screen	37
4.3.2.2 Advanced Screen	39
4.3.2.2.1 Processor Configuration Screen	40
4.3.2.2.2 Memory Configuration Screen	42
4.3.2.2.3 SATA Controller Configuration Screen	44
4.3.2.2.4 Serial Ports Screen	45
4.3.2.2.5 USB Configuration Screen	46
4.3.2.2.6 PCI Screen	48
4.3.2.3 Security Screen	49
4.3.2.4 Server Management Screen	51
4.3.2.4.1 Console Redirection Screen	52
4.3.2.4.2 System Information Screen	54
4.3.2.5 Boot Options Screen	55
4.3.2.5.1 Hard Disk Order Screen	56
4.3.2.5.2 CDROM Order Screen	56
4.3.2.5.3 Floppy Order Screen	57
4.3.2.5.4 Network Device Order Screen	58
4.3.2.5.5 BEV Device Order Screen	58
4.3.2.6 Boot Manager	59
4.3.2.7 Error Manager Screen	60
4.3.2.8 Exit Screen	60
4.4 Loading BIOS Defaults	62
4.5 Multiple Boot Blocks	62
4.6 Recovery Mode	63
4.7 OEM Logo	63
5. Platform Management	65
5.1 Platform Management Features	65
5.2 Power System	66
5.2.5.1 Power Button Signal	68
5.2.5.2 Chipset Sleep S4/S5	69
5.2.5.3 Power-On Enable	69
5.2.5.4 Power-down Disable	69
5.3 Advanced Configuration and Power Interface (ACPI)	70
5.4 System Reset Control	71
5.5 BMC Reset Control	72
5.6 System Initialization	72
5.6.2.1 Watchdog Timer Timeout Reason Bits	73
5.7 Integrated Front Panel User Interface	74
5.7.3.1 Chassis Intrusion	75
5.7.3.2 Power Button	75
5.7.3.3 Reset Button	75
5.8 Private Management I2C Buses	76
5.9 Watchdog Timer	76
5.10 BMC Internal Timestamp Clock	76
5.11 System Event Log (SEL)	77
5.12 Sensor Data Record (SDR) Repository	77
5.13 Field Replaceable Unit (FRU) Inventory Device	78
5.14 Sensor Rearm Behavior	79
5.15 Processor Sensors	80
5.15.1.1 ThermTrip Monitoring	80
5.15.1.2 IERR Monitoring	81
5.15.2.1 PECI Interface	81
5.16 Standard Fan Management	81
5.17 Power Unit Management	83
5.18 BMC Self Test	84
5.19 Messaging Interfaces	84
5.19.6.1 LPC/KCS Interface	85
5.19.6.2 Receive Message Queue	86
5.19.6.3 SMS/SMM Status Register	86
5.19.6.4 Server Management Software (SMS) Interface	86
5.19.6.5 SMM Interface	87
5.19.8.1 Serial-over-LAN (SOL 2.0)	88
5.20 Event Filtering and Alerting	88
5.21 Sensor Support	89
5.22 BIOS-BMC interactions	95
5.23 Platform Management Features Implemented by BIOS	95
5.23.2.1 Serial Configuration Settings	96
5.23.2.2 Keystroke Mappings	96
5.23.2.2.1 Standalone <Esc> Key for Headless Operation	96
5.23.2.3 Limitations	97
5.23.2.4 Interface to Server Management	97
5.23.3.1 Channel Access Modes	97
5.23.3.2 Interaction with BIOS Console Redirection	97
5.23.3.3 SOL, EMP and Console Redirection Use Case Model	98
5.23.4.1 PXE BIOS Support	100
5.23.6.1 Password Clear Jumper	101
6. Error Reporting and Handling	102
6.1 Fault Resilient Booting	102
6.2 Error Handling and Logging	103
6.2.2.1 PCI Bus Error	103
6.2.2.2 PCI Express* Errors	103
6.2.2.3 Processor Bus Error	104
6.2.2.4 Memory Bus Error	104
6.2.2.5 Operating System Watchdog Failure	104
6.2.2.6 Boot Event	104
6.2.3.1 Memory Error Events	105
6.2.3.2 Examples of Event Data Field Contents for Memory Errors	106
6.2.3.3 PCI Error Events	106
6.2.3.4 Examples of Event Data Field Contents for PCI Errors	107
6.2.3.5 FRB-2 Error Events	107
6.2.4.1 No Real-Time Clock (RTC) Access	108
6.3 Error Messages and Error Codes	109
7. Connectors and Jumper Blocks	116
7.1 Power Connectors	116
7.2 PCI Express* x16 Connector	116
7.3 SMBus Connector	118
7.4 Front Panel Connector	118
7.5 I/O Connectors	119
7.6 Fan Headers	122
7.7 Chassis Intrusion Header	122
7.8 Jumper Blocks	123
8. Design and Environmental Specifications	124
8.1 Server Board Design Specification	124
8.2 Product Regulatory Compliance	124
8.3 Electromagnetic Compatibility Notices	127
Glossary	128

Match case Limit results 1 per page

Platform Management

Intel® Server Board X38ML

Revision 1.3

Intel order number E15331-006

5.8

Private Management I

C Buses

The BMC controls multiple private I

C buses. The BMC is the sole master on these buses.

External agents must use the BMC’s

Master Write/Read I

command if they require direct

communication with a device on any of these buses. Only FRU devices are accessible in this

manner. Sensor devices should not be directly accessed by BMC clients.

5.9

Watchdog Timer

The BMC implements a fully IPMI 2.0-compatible watchdog timer. See the IPMI 2.0

specification. A watchdog pre-timeout interrupt signal assertion is not supported.

5.10

BMC Internal Timestamp Clock

The BMC maintains a 4-byte internal timestamp clock that subsystems, such as the SEL, use.

The timestamp value is derived from an RTC element internal to the BMC.

This internal timestamp clock is read and set using the

Get SEL Time

and

Set SEL Time

commands, respectively. You can also use the

Get SDR Time

command to read the timestamp

clock. The IPMI 2.0 specification specifies the commands and the IPMI time format.

5.10.1

BMC Clock Initialization

During system initialization the BMC cannot guarantee the validity of its internal timestamp, so it

resets its clock counter to zero. The BMC attempts to retrieve the current time from an internal

battery-backed RTC element. If the RTC time is in the pre-init range of 0 to 0x20000000, then

the BMC ignores it and continues counting from zero, and any SEL events have pre-init

timestamps relative to the approximate time of the BMC initialization.

Whenever the BMC receives the

Set SEL Time

command, it updates the integrated RTC value.

This helps ensure the BMC internal clock maintains synchronization with the system clock

across BMC initializations. Using the

Set SEL Time

command to force the BMC to a pre-init

timestamp causes the RTC to be updated with the same value. Unless the

Set SEL Time

command is sent with a valid time before the next BMC initialization, the BMC ignores the pre-

init time stored in the RTC.

5.10.2

System Clock Synchronization

The BMC does not have direct access to the system clock used by BIOS and the operating

system. The BIOS must send the

Set SEL Time

command with the current system time to the

BMC during the system Power-on Self-Test (POST). Synchronization during very early POST is

preferred, so any SEL entries recorded during system boot have an accurate time stamp.

If the time is modified through an operating system interface, then the BMC’s time is not

synchronized until the next system reboot.