Nintendo 1504166 Programming Manual - Page 123

however, Direct Sound FIFO Transfer mode will be cancelled so that the value of

Get Nintendo 1504166 - Game Boy Advance SP Edition Console PDF manuals and user guides View all Nintendo 1504166 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 123 highlights

AGB Programming Manual DMA Transfer 3.Write the following settings in 16-bit blocks to the DMA control register and stop the DMA. -DMA enabled flag : -DMA start timing : -Data request transfer flag of the Game Pak side : -DMA repeat : -Other control bits : 0 (Disabled) 00 0 (DMA3 only) 0 No change *Note Please note that the DMA may be started one extra time due to procedure 1 above. 2-2) How to stop a DMA repeat in the Direct Sound FIFO Transfer mode. 1.Write the following settings in 32-bit blocks to the DMA control register and Word count register. -DMA Word count register - Word count : 0004h -DMA control register - DMA enabled flag : - DMA start timing : - DMA transfer type : - DMA repeat : - Destination address control flag : - Other control bits : 1 (Enabled) 00 (Start immediately) 1 (32 bit transfer mode) 0 (OFF) 10 (Fixed) No change However, when the value of the DMA word count register is already set to 0004h, the procedure is executed by writing in 16-bit width to the DMA control register. * It is possible to disable the next repeated DMA by setting the DMA to start immediately; however, Direct Sound FIFO Transfer mode will be cancelled so that the value of the Word count register will be used. Therefore, the value of the Word count register needs to be set to 0004h.* Similarly, the setting of destination address control flag will be used, so the value of 10 (destination address fixed) needs to be set, too.* *We recommend that the transfer type, destination address control flag, and the word count are initially set to the above setting. (i.e., transfer type = 1, destination address control flag = 10, and word count = 0004h). 2.Run a process of 4 clocks or more. Example: (Three NOP commands or one LDR command) + the 1st clock of the STR command by the following procedure (3) equals a total of 4 clocks. (Data is actually written at the 2nd clock of the STR command.) ©1999 - 2001 Nintendo of America Inc. 123 D.C.N. AGB-06-0001-002B4

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
AGB Programming Manual
DMA Transfer
©1999 - 2001 Nintendo of America Inc.
123
D.C.N. AGB-06-0001-002B4
3.Write the following settings in 16-bit blocks to the DMA control register and stop the
DMA.
-DMA enabled flag :
0 (Disabled)
-DMA start timing :
00
-Data request transfer flag of the Game Pak side :
0 (DMA3 only)
-DMA repeat :
0
-Other control bits :
No change
*Note
Please note that the DMA may be started one extra time due to procedure 1 above.
2-2) How to stop a DMA repeat in the Direct Sound FIFO Transfer mode.
1.Write the following settings in 32-bit blocks to the DMA control register and Word
count register.
-DMA Word count register
-
Word count :
0004h
-DMA control register
- DMA enabled flag :
1 (Enabled)
- DMA start timing :
00 (Start immediately)
- DMA transfer type :
1 (32 bit transfer mode)
- DMA repeat :
0 (OFF)
- Destination address control flag :
10 (Fixed)
- Other control bits :
No change
However, when the value of the DMA word count register is already set to 0004h, the
procedure is executed by writing in 16-bit width to the DMA control register. *
It is possible to disable the next repeated DMA by setting the DMA to start immediately;
however, Direct Sound FIFO Transfer mode will be cancelled so that the value of the
Word count register will be used.
Therefore, the value of the Word count register needs
to be set to 0004h.*
Similarly, the setting of destination address control flag will be used, so the value of 10
(destination address fixed) needs to be set, too.*
*We recommend that the transfer type, destination address control flag, and the word
count are initially set to the above setting. (i.e., transfer type = 1, destination address
control flag = 10, and word count = 0004h).
2.Run a process of 4 clocks or more.
Example:
(Three NOP commands or one LDR command) + the 1st clock of the STR
command by the following procedure (3) equals a total of 4 clocks.
(Data is actually written at the 2nd clock of the STR command.)