Nintendo 1504166 Programming Manual - Page 85

Direct Sounds A and B, Using sound control register SOUNDCNT_H, do a 0 clear with FIFO A and FIFO

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AGB Programming Manual Sound 10.2 Direct Sounds A and B Direct sounds have 2 channels, A and B. Linear 8-bit audio data can be played back. The audio data are set to a bias level of 00h and are 8-bit data (+127 to -128), obtained by 2's complement. Audio data are transferred sequentially to the sound FIFO (8-word capacity), using the sound FIFO transfer mode of DMA 1 and 2. The sampling rate can be set to an arbitrary value using timers 0 and 1. Sound FIFO Input Register Address 0A0h 0A4h Register FIFO_A_L FIFO_B_L 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Attributes Initial Value Sound Data 1 Sound Data 0 W - Address 0A2h 0A6h Register FIFO_A_H FIFO_B_H 15 14 13 12 11 10 Sound Data 3 09 08 07 06 05 04 03 02 Sound Data 2 01 00 Attributes Initial Value W - Sound Data All sounds are PWM modulated (refer to 10.8 "Sound PWM Control") at the final portion of the Sound Circuit. Therefore, if you match the 8 bit audio data sampling frequency and the timer settings with the PWM modulation sampling frequency, a clean sound can be produced. The following operations are repeated for direct sound. Preparing to Use Direct Sound 1. Using sound control register SOUNDCNT_H (refer to 10.7 "Sound Control"), select the timer channel to be used (0 or 1). 2. Using sound control register SOUNDCNT_H, do a 0 clear with FIFO A and FIFO B, and initialize the sequencer. 3. In cases of producing a sound immediately after starting the direct sound, write the first 8 bits of linear audio data to the FIFO with a CPU write. 4. Specify the transfer mode for DMA 1 or 2 (see 12.2 "DMA 1 and 2"). 5. Specify the direct sound outputs settings in the sound control register. 6. Start the timer. ©1999 - 2001 Nintendo of America Inc. 85 D.C.N. AGB-06-0001-002B4

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AGB Programming Manual
Sound
©1999 - 2001 Nintendo of America Inc.
85
D.C.N. AGB-06-0001-002B4
10.2 Direct Sounds A and B
Direct sounds have 2 channels, A and B.
Linear 8-bit audio data can be played back.
The audio data are set to a bias level of 00h and are 8-bit data (+127
to
-128), obtained
by 2’s complement.
Audio data are transferred sequentially to the sound FIFO (8-word capacity), using the
sound FIFO transfer mode of DMA 1 and 2.
The sampling rate can be set to an arbitrary value using timers 0 and 1.
Sound FIFO Input Register
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
FIFO_A_L
FIFO_B_L
0A0h
0A4h
-
W
Address
Register
Attributes
Initial Value
Sound Data 1
Sound Data 0
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
FIFO_A_H
FIFO_B_H
0A2h
0A6h
-
W
Sound Data 3
Sound Data 2
Address
Register
Attributes
Initial Value
Sound Data
All sounds are PWM modulated (refer to 10.8 “Sound PWM Control”) at the final
portion of the Sound Circuit.
Therefore, if you match the 8 bit audio data sampling
frequency and the timer settings with the PWM modulation sampling frequency, a
clean sound can be produced.
The following operations are repeated for direct sound.
Preparing to Use Direct Sound
1.
Using sound control register SOUNDCNT_H (refer to 10.7 “Sound Control”),
select the timer channel to be used (0 or 1).
2.
Using sound control register SOUNDCNT_H, do a 0 clear with FIFO A and FIFO
B, and initialize the sequencer.
3.
In cases of producing a sound immediately after starting the direct sound, write
the first 8 bits of linear audio data to the FIFO with a CPU write.
4.
Specify the transfer mode for DMA 1 or 2 (see 12.2 “DMA 1 and 2”).
5.
Specify the direct sound outputs settings in the sound control register.
6.
Start the timer.