Nintendo 1504166 Programming Manual - Page 157
Interrupt Control, Interrupt Master Enable Register
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AGB Programming Manual Interrupt Control 15 Interrupt Control AGB can use 14 types of maskable hardware interrupts. If an interrupt request signal is received from a hardware item, the corresponding interrupt request flag is set in the IF register. Masking can be performed individually for interrupt request signals received from each hardware item by means of the interrupt request flag register IE. 1) Interrupt Master Enable Register The entire interrupt can be masked. When this flag is 0, all interrupts are disabled. When 1, the setting for interrupt enable register IE is enabled. Adderess Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Attributes Initial Value 208h IME R/W 0000h Interrupt Master Enable Flag 2) Interrupt Enable Register With the interrupt enable register, each hardware interrupt can be individually masked. Address Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Attributes Initial Value 200h IE DMA DMA DMA DMA 32 1 0 Timer Timer Timer Timer 3 21 0 H V R/W 0000h DMA Key Game Pak(DREQ/IREQ) Rendering Blank V Counter Match Timer Serial Communication/General Purpose Communication/JOY Bus Communication/ UART Communication By resetting the bit, the corresponding interrupt can be prohibited. Setting this to 1 enables the corresponding interrupt. ©1999 - 2001 Nintendo of America Inc. 157 D.C.N. AGB-06-0001-002B4