Nintendo 1504166 Programming Manual - Page 158
Interrupt Request Register, Cautions regarding clearing IME and IE], When multiple interrupts are used
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AGB Programming Manual Interrupt Control 3) Interrupt Request Register When an interrupt request signal is generated from each hardware device, the corresponding interrupt request flag is set in the IF Register. Address 202h Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Attributes Initial Value IF DMA DMA DMA DMA 3 2 10 Timer Timer Timer Timer 32 1 0 H V R 0000h Rendering Blank V Counter Matching Timer DMA Serial Communication/General Purpose Communication/JOY Bus Communication/UART Communication Key Game Pak(DREQ/IREQ) If a 1 is written to the bit which the interrupt request flag is set in, that interrupt request flag can be reset [Cautions regarding clearing IME and IE] A corresponding interrupt could occur even while a command to clear IME or each flag of the IE register is being executed. When clearing a flag of IE, you need to clear IME in advance so that mismatching of interrupt checks will not occur. When multiple interrupts are used When the timing of clearing of IME and the timing of an interrupt agree, multiple interrupts will not occur during that interrupt. Therefore, set (enable) IME after saving IME during the interrupt routine. ©1999 - 2001 Nintendo of America Inc. 158 D.C.N. AGB-06-0001-002B4