Toshiba Portege M100 Maintenance Manual - Page 22
System Unit Block Diagram, Hardware Overview, PCI Rev2.2 Interface 6 PCI REQ/CNT Paris
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1.2 System Unit Block Diagram 1 Hardware Overview The system unit is composed of the following major components: q Processor • A 1.20GHz Intel Pentium® M Processor 1.2GHz - Processor core speed:1.20GHz at 1.20V - Integrated L1 cache memory: 64KB - Integrated L2 cache memory: 1MB - Integrated NDP q PCI Chip Set • North Bridge: Intel MontaraGM Features: - Supports Banias Processor System Bus. - DRAM Controller supporting DDR200/DDR266 - AGP Interface (AGP R2.0) - Hub Link Interface - Internal Graphics - 732-ball 37.5×37.5mm FC-BGA Package • South Bridge: Intel ICH4-M Features: - Hub Link Interface - PCI Rev2.2 Interface (6 PCI REQ/CNT Paris) - Bus master IDE Controller (Ultra ATA 100/66/33) - USB 1.1/2.0 controller with6 ports - I/O APIC (ACPI 1.0b compatible) - SM Bus 2.0 controller - FWH Interface (BIOS) - LPC Interface (EC/KBC, Supper I/O) - IRQ controller - Serial Interrupt function - Power Management function - Supports Deeper Sleep (4). - Suspend/Resume control - AC'97 2.2 Interface - Internal RTC - 421-ball (31mm×31mm) BGA Package PORTEGE M100 Maintenance Manual (960 -452) 1-7