Toshiba Portege M100 Maintenance Manual - Page 23
One M306K7F8LRP chip functions as both KBC and EC., Hardware Overview, System Unit Block Diagram
View all Toshiba Portege M100 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 23 highlights
1 Hardware Overview 1.2 System Unit Block Diagram q PC Card Controller: • YEBISU3S Features: - PCI Interface (PCI Rev. 2.2) - CardBus Controller (Yenta2 Ver. 2.2) - SD IO card controller (Ver. 1.0) - SD card controller (SDHC Ver. 1.2) - SIO controller - Docking Station Interface Q-SW control, Rest control - External Device Interface q VGA Controller: inside in the North Bridge. q Memory Two DDR SO-DIMM slots are available for 128,256,512MB and 1GB memory modules, consisting of SDRAM chips. • Supports CL2/2.5 • Supports PC2100 • 128/256/512 MB, 1GB selectable - 128MB: 256Mbit (16M × 16bit) chips ×4 - 256MB: 256Mbit (16M × 16bit) chips ×8 - 512MB: 512Mbit (32M × 16bit) chips ×16 - 1GB: 512Mbit (64M × 8 bit) chips × 16 q Super I/O • One SMSC LPC47n227-MN-B is used. q IPSC • TWM7000 (HOSIDEN made) q KBC/EC (Keyboard Controller/Embedded Controller) • One M306K7F8LRP chip functions as both KBC and EC. q PSC (Power Supply Controller) • One TMP87PM48U chip is used. • This controller controls the power sour ces. 1-8 PORTEGE M100 Maintenance Manual (960-452)