Dell Broadcom NetXtreme Family of Adapters Broadcom NetXtreme 57XX User Guide - Page 127

C3 DMA C4 MII C5 VPD This test tests both high-priority direct memory access (DMA) and low-priority DMA. The test moves data from the host memory to the adapter SRAM and verifies the data. The test then moves data back to the host memory to again verify the data. The medium independent interface (MII) test function is identical to that of the Control Register Test (A2). Each register specified in the configuration contents defines the read-only and read/write bits. The test writes 0s and 1s to the test bits to ensure that the read-only bit values are not changed and that the read/write bits are changed. The test attempts to read the register configuration file (Miireg.txt) for the register definitions. If the file does not exist, the following table is used: Offset Read-Only Mask Read/Write Mask 0x00 0x0000 0x7180 0x02 0xFFFF 0x0000 0x03 0xFFFF 0x0000 0x04 0x0000 0xFFFF 0x05 0xEFFF 0x0000 0x06 0x0001 0x0000 0x07 0x0800 0xB7FF 0x08 0xFFFF 0x0000 0x09 0x0000 0xFF00 0x0A 0x7C00 0x0000 0x10 0x0000 0xFFBF 0x11 0x7C00 0x0000 0x19 0x7C00 0x0000 0x1E 0x0000 0xFFFF 0x1F 0x0000 0xFFFF The VPD test first saves the contents of the vital product data (VPD) memory before performing the test. The test then writes 1 of the 5 test data patterns (0xFF, 0xAA, 0x55, increment data, or decrement data) into VPD memory. By default, an incremental data pattern is used. The test writes and reads back the data for the entire test range, and then restores the original contents of the VPD memory. Reset Test. This test sets the reset bit and polls for self-clearing bits. This test verifies the reset value of the registers. Event Mapping Test. This test sets the SMB_ATTN bit. By changing ASF_ATTN_ LOC bits, the test verifies the mapping bits in TX_CPU or RX_CPU event bits. Counter Test C6 ASF Hardware Clears WG_TO, HB_TO, PA_TO, PL_TO, RT_TO bits (by setting the bits) and ensures that the bits clear. Clears the timestamp counter. Writes a 1 to each of the PL, PA, HB, WG, RT counters. Sets the TSC_EN bit. Polls each PA_TO bit and counts up to 50. Checks if the PL_TO bit is set at the end of the count to 50. Continues to count up to 200. Checks if all other TO bits are set and verifies if the timestamp counter is incremented. C7 Expansion ROM This test tests the ability to enable, disable, and access the expansion read-only memory (ROM) on the adapter. C8 CPU Fetch This test tests the PCU instruction fetch logic 100 times. Group D: Driver Associated Tests This test is an internal loopback data transmit/receive test. It initializes the medium access control D1 MAC Loopback (MAC) into an internal loopback mode and transmits 100 packets. The data should be routed back to the receive channel and received by the receive routine, which verifies the integrity of data. A 100-Mbit/s data rate is used for this test unless Gigabit Ethernet is enabled. D2 PHY Loopback This test is same as the MAC loopback test (D1), except that the data is routed back via a physical layer device (PHY). A 100-Mbit/s data rate is used for this test unless Gigabit Ethernet is enabled. D5 MII Miscellaneous This test tests the autopolling and PHY interrupt capabilities. These are functions of the PHY. D6 MSI This test tests the message signal interrupt (MSI) capability of the adapter. Refer to PCI Specification, version 2.3, for the MSI definition. Diagnostic Test Messages /* 0 */ "PASS", /* 1 */ "Got 0x%08X @ 0x%08X. Expected 0x%08X", /* 2 */ "Cannot perform task while chip is running", /* 3 */ "Invalid NIC device", /* 4 */ "Read-only bit %s got changed after writing zero at offset 0x%X",