AMD AMD-K6-2/500AFX Data Sheet
AMD AMD-K6-2/500AFX - MHz Processor Manual
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- AMD AMD-K6-2/500AFX | Data Sheet - Page 1
Preliminary Information AMD-K6®-2 Processor Data Sheet - AMD AMD-K6-2/500AFX | Data Sheet - Page 2
in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a time without notice. Trademarks AMD, the AMD logo, K6, 3DNow!, and combinations thereof, K86, and Super7 are trademarks, and AMD-K6 and RISC86 are registered - AMD AMD-K6-2/500AFX | Data Sheet - Page 3
3 Super7™ Platform Enhancements 3 Super7™ Platform Advantages 4 2 Internal Architecture 5 2.1 Introduction 5 2.2 AMD-K6®-2 Processor Microarchitecture Overview 5 Enhanced RISC86® Microarchitecture 6 2.3 Cache, Instruction Prefetch, and Predecode Bits 9 Cache 9 Prefetching 10 Predecode Bits - AMD AMD-K6-2/500AFX | Data Sheet - Page 4
)-Model 8/[F:8] . . 51 UC/WC Cacheability Control Register (UWCCR)52 Processor State Observability Register (PSOR 53 Page Flush/Invalidate Register (PFIR 53 3.3 Instructions Supported by the AMD-K6®-2 Processor . . . . . 54 4 Signal Descriptions 83 4.1 Signal Terminology 83 4.2 A20M# (Address - AMD AMD-K6-2/500AFX | Data Sheet - Page 5
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents 4.33 LOCK# (Bus Lock 110 4.34 M/IO# (Memory or I/O 111 4.35 NA# (Next Address 112 4.36 NMI (Non-Maskable Interrupt 112 4.37 - AMD AMD-K6-2/500AFX | Data Sheet - Page 6
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD-Initiated 173 BRDYC 173 6.2 RESET Requirements 174 6.3 State of Processor After RESET 174 Output Signals 174 Registers 174 6.4 State of Processor After INIT 177 7 Cache Organization 179 7.1 MESI States in - AMD AMD-K6-2/500AFX | Data Sheet - Page 7
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents WBINVD and INVD 196 Cache- External Logic Support of Floating-Point Exceptions . . . . . 207 9.2 Multimedia and 3DNow!™ Execution Units 209 9.3 Floating-Point and MMX™/3DNow!™ Instruction Compatibility 209 - AMD AMD-K6-2/500AFX | Data Sheet - Page 8
AMD-K6®-2 Processor AHX, 400AFQ, and AFR 253 Operating Ranges 253 Absolute Ratings 254 DC Characteristics 254 Power Dissipation 257 14.2 Electrical Data for OPN Suffixes AGR, AFX, and 400AFR for 100-MHz Bus Operation 268 16.3 Clock Switching Characteristics for 66-MHz Bus Operation - AMD AMD-K6-2/500AFX | Data Sheet - Page 9
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 16.5 Output Delay Timings for 100-MHz Bus Operation 270 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 272 16.7 Output Delay Timings for 66-MHz Bus Operation 274 16.8 Input Setup and Hold Timings for 66- - AMD AMD-K6-2/500AFX | Data Sheet - Page 10
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 x Contents - AMD AMD-K6-2/500AFX | Data Sheet - Page 11
2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Figures Figure 1. AMD-K6®-2 Processor Block Diagram 7 Figure 2. Cache Sector Organization 10 Figure 3. Figure 4. Figure 5. The Instruction Buffer 11 AMD-K6®-2 Processor Decode Logic 12 AMD-K6®-2 Processor Scheduler 15 - AMD AMD-K6-2/500AFX | Data Sheet - Page 12
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 37. Memory Model 8/[F:8] . . 52 Figure 49. UC/WC Cacheability Control Register (UWCCR 52 Figure 50. Processor State Observability Register (PSOR 53 Figure 51. Page Flush/Invalidate Register (PFIR 53 Figure 52. - AMD AMD-K6-2/500AFX | Data Sheet - Page 13
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Figures Figure 75. Cacheability Control Register (UWCCR)- MSR C000_0085h (Model 8/[F:8 204 Figure 84. External Logic for Supporting Floating-Point Exceptions. . . 208 Figure 85. SMM Memory 213 Figure 86. TAP - AMD AMD-K6-2/500AFX | Data Sheet - Page 14
292 Figure 110. Airflow Path in a Dual-Fan System 293 Figure 111. Airflow Path in an ATX Form-Factor System 293 Figure 112. AMD-K6®-2 Processor Top-Side View 295 Figure 113. AMD-K6®-2 Processor Pin-Side View 296 Figure 114. 321-Pin Staggered CPGA Package Specification 300 xiv List of Figures - AMD AMD-K6-2/500AFX | Data Sheet - Page 15
Summary of Exceptions and Interrupts 49 AMD-K6®-2 Processor Model 8/[F:8] MSRs 50 Extended Feature Enable Register (EFER)- Model 8/[F:8] Definition 51 Integer Instructions 55 Floating-Point Instructions 74 MMX™ Instructions 78 3DNow!™ Instructions 81 Processor-to-Bus Clock Ratios 92 Output - AMD AMD-K6-2/500AFX | Data Sheet - Page 16
AMD-K6®-2 Processor Data Sheet Preliminary Information Supported Tap Instructions 231 DR7 LEN and RW Definitions 241 Operating Ranges for OPN Suffixes AHX, 400AFQ, and AFR 253 Absolute Ratings for OPN Suffixes AHX, 400AFQ, and AFR 254 DC Characteristics for OPN Suffixes AHX, 400AFQ, and AFR - AMD AMD-K6-2/500AFX | Data Sheet - Page 17
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 72. Table 73. Table 74. Package Thermal Specification for OPN Suffixes AGR, AFX, and 400AFR 287 321-Pin Staggered CPGA Package Specification 299 Valid Ordering Part Number Combinations 301 List of Tables - AMD AMD-K6-2/500AFX | Data Sheet - Page 18
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xviii List of Tables - AMD AMD-K6-2/500AFX | Data Sheet - Page 19
for OPN Suffixes AHX, 400AFQ, and AFR," on page 257 and Table 71, "Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR," on page 285. Added 550 MHz specifications. Added MOV to/from CRx, RDMSR, RDTSC, RSM, and WRMSR J instructions to Table 14, "Integer Instructions," on page 55 - AMD AMD-K6-2/500AFX | Data Sheet - Page 20
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xx Revision History - AMD AMD-K6-2/500AFX | Data Sheet - Page 21
support s 3DNow!™ Technology x Additional instructions to improve 3D graphics and multimedia performance x Separate multiplier and ALU for superscalar instruction execution s Compatible with Super7™ platform x Leverages high-speed 100-MHz processor bus x Accelerated Graphic Port (AGP) support - AMD AMD-K6-2/500AFX | Data Sheet - Page 22
-of-the-art design techniques to achieve leading-edge performance. Advanced design techniques implemented in the AMD-K6-2 processor include multiple x86 instruction decode, single-clock internal RISC operations, ten execution units that support superscalar operation, out-of-order execution, data - AMD AMD-K6-2/500AFX | Data Sheet - Page 23
L3 cache-The Super7 platform has the 'headroom' to support higher-performance AMD-K6 processors, with clock speeds scaling to 550 MHz and beyond. The Super7 platform also supports the AMD-K6-III processor which features a full-speed, internal backside 256-Kbyte L2 cache designed to enable new - AMD AMD-K6-2/500AFX | Data Sheet - Page 24
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Super7™ Platform Advantages The Super7 platform has the following advantages: s Delivers performance and features competitive with alternate platforms at the same clock speed, and at a significantly lower cost s Takes - AMD AMD-K6-2/500AFX | Data Sheet - Page 25
s o r i s t h e industry-standard x86 instruction set. The term microarchitecture refers to the design techniques used in the processor to reach the target cost, performance, and functionality goals. The AMD-K6 family of processors are based on a sophisticated RISC core known as the Enhanced RISC86 - AMD AMD-K6-2/500AFX | Data Sheet - Page 26
execution units that support superscalar operation - multiple decode, execution, and retirement-of x86 instructions. These elements are packed into an aggressive and highly efficient six-stage pipeline. AMD-K6®-2 Processor Block Diagram. As shown in Figure 1 on page 7, the high-performance, out-of - AMD AMD-K6-2/500AFX | Data Sheet - Page 27
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 100 MHz Super7™ Bus Interface Predecode Logic 32-KByte Level-One Instruction Cache 20-KByte Predecode Cache 64-Entry ITLB Level-One Cache Controller Out-of-Order Execution Engine Six RISC86 ® Operation Issue 16- - AMD AMD-K6-2/500AFX | Data Sheet - Page 28
12 x86 instructions. This buffer size (24) is perfectly matched to the processor's six-stage specifically for MMX and 3DNow! operations. There are 9 MMX/3DNow! committed or architectural registers plus 12 MMX/3DNow 29. Branch Logic. The AMD-K6-2 processor is designed with highly sophisticated - AMD AMD-K6-2/500AFX | Data Sheet - Page 29
specifically designed for optimizing CALL and RETURN pairs. In summary, the AMD-K6-2 processor uses dynamic branch logic to minimize delays due to the branch instructions that are common in x86 software. 3DNow!™ Technology. AMD has taken a lead role in improving the multimedia and 3D capabilities - AMD AMD-K6-2/500AFX | Data Sheet - Page 30
. The AMD-K6-2 processor conditionally performs cache prefetching instruction format is defined in Table 17, "3DNow!™ Instructions," on page 81. For more detailed information, see the 3DNow!™ Technology Manual, order# 21928. Decoding x86 instructions is particularly difficult because the instructions - AMD AMD-K6-2/500AFX | Data Sheet - Page 31
2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 2.4 Instruction Fetch and Decode Instruction Fetch The processor can fetch up to 16 bytes per clock out of the instruction cache or branch target cache. The fetched information is placed into a 16-byte instruction buffer that feeds - AMD AMD-K6-2/500AFX | Data Sheet - Page 32
-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Instruction Decode The AMD-K6-2 processor decode logic is designed to decode multiple x86 instructions per clock (see Figure 4). The decode logic accepts x86 instruction bytes and their predecode bits from the instruction - AMD AMD-K6-2/500AFX | Data Sheet - Page 33
Information AMD-K6®-2 Processor Data Sheet Chapter 2 The AMD-K6-2 processor uses a combination of decoders to convert x86 instructions and semi-commonly-used x86 instructions that are up to seven bytes long are handled by the long decoder. The long decoder only performs one decode per clock and - AMD AMD-K6-2/500AFX | Data Sheet - Page 34
advantage is due to the fact that the scheduler operates on the RISC86 operations in parallel and allows the AMD-K6-2 processor to perform dynamic on-the-fly instruction code scheduling for optimized execution. Although the scheduler can issue RISC86 operations for out-of-order execution, it always - AMD AMD-K6-2/500AFX | Data Sheet - Page 35
AMD-K6®-2 Processor Scheduler 2.6 Execution Units The AMD-K6-2 processor contains ten parallel execution units-store, load, integer X ALU, integer Y ALU, MMX ALU (X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow stage pipelined designs. The store unit performs data writes and register calculation for - AMD AMD-K6-2/500AFX | Data Sheet - Page 36
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Register X and Y Pipelines 16 The Integer X execution unit can operate on all ALU operations, multiplies, divides (signed and unsigned), shifts, and rotates. The Integer Y execution unit can operate on the basic word - AMD AMD-K6-2/500AFX | Data Sheet - Page 37
). When a conditional branch is not taken, the processor simply continues decoding and executing the next instructions in memory. Typical applications have up to 10% of unconditional branches and another 10% to 20% conditional branches. The AMD-K6-2 processor branch logic has been designed to handle - AMD AMD-K6-2/500AFX | Data Sheet - Page 38
16-byte branch target cache, a 16-entry return address stack, and a branch execution unit. The AMD-K6-2 processor handles unconditional branches without any penalty by redirecting instruction fetching to the target address of the unconditional branch. However, conditional branches require the use of - AMD AMD-K6-2/500AFX | Data Sheet - Page 39
until all speculatively executed conditional branch instructions are resolved. When a prediction is incorrect, the processor backs out to the point of the mispredicted branch instruction and restores all registers. The AMD-K6-2 processor can support up to seven outstanding branches. Chapter - AMD AMD-K6-2/500AFX | Data Sheet - Page 40
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 20 Internal Architecture Chapter 2 - AMD AMD-K6-2/500AFX | Data Sheet - Page 41
Environment This chapter provides a general overview of the AMD-K6-2 processor's x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the AMD-K6-2 architecture and design implementation. The stepping of the Model - AMD AMD-K6-2/500AFX | Data Sheet - Page 42
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 General-Purpose Registers 31 The eight 32-bit x86 general-purpose registers are used to hold integer data or memory pointers used by instructions the stack segment In order to support byte and word operations, EAX, - AMD AMD-K6-2/500AFX | Data Sheet - Page 43
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Integer Data Types Byte Integer Table 3. General-Purpose Register Doubleword, Word, and Byte Names 32-Bit Name (Doubleword) EAX EBX ECX EDX EDI - AMD AMD-K6-2/500AFX | Data Sheet - Page 44
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Segment Registers registers. Table 4. Segment Registers Segment Register Segment Register Function CS Code segment, where instructions are located DS Data segment, where data is located ES Data segment, where data - AMD AMD-K6-2/500AFX | Data Sheet - Page 45
manipulated, but can be altered by modifying return pointers when a JMP or CALL instruction is used. Floating-Point Registers The floating-point execution unit in the AMD-K6-2 processor is designed to perform mathematical operations on non-integer numbers. This floating-point unit conforms to the - AMD AMD-K6-2/500AFX | Data Sheet - Page 46
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 79 78 Sign The eight floating-point registers are physically 80 bits wide and labeled FPR0-FPR7. Figure - AMD AMD-K6-2/500AFX | Data Sheet - Page 47
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet The FPU control word register allows a programmer to manage the FPU processing options. Figure 13 shows the format of this register. 15 14 - AMD AMD-K6-2/500AFX | Data Sheet - Page 48
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Floating-Point Register Data Types Floating-point registers use four different types of data - packed decimal, single-precision - AMD AMD-K6-2/500AFX | Data Sheet - Page 49
. For more information, see the AMD-K6® Processor Multimedia Technology Manual, order# 20726 and the 3DNow!™ Technology Manual, order# 21928. 63 0 mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 Figure 17. MMX™/3DNow!™ Registers MMX™ Data Types For the MMX instructions, the MMX registers use three types - AMD AMD-K6-2/500AFX | Data Sheet - Page 50
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Packed 63 32 31 0 Doubleword 1 Doubleword 0 Figure 18. MMX™ Data Types 3DNow!™ Data Types For 3DNow! instructions, the MMX/3DNow! registers use packed single-precision real data. Figure 19 shows the format of - AMD AMD-K6-2/500AFX | Data Sheet - Page 51
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet EFLAGS Register The EFLAGS register provides for three different types of flags - system, control, and status. The system flags provide operating system controls, - AMD AMD-K6-2/500AFX | Data Sheet - Page 52
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Control Registers The five control registers contain system control bits and pointers. Figures 21 through 25 show the - AMD AMD-K6-2/500AFX | Data Sheet - Page 53
21850J/0-February 2000 31 Preliminary Information AMD-K6®-2 Processor Data Sheet 0 Reserved Figure 24. Control Register 1 ( Extension Type 4 TS Task Switched 3 EM Emulation 2 MP Monitor Co-processor 1 PE Protection Enabled 0 Figure 25. Control Register 0 (CR0) Chapter 3 Software - AMD AMD-K6-2/500AFX | Data Sheet - Page 54
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Debug Registers Figures 26 through 29 show the 32-bit debug registers supported by the processor. Symbol LEN 3 R/W 3 LEN 2 R/W 2 LEN 1 R/W 1 LEN 0 R/W 0 Description Length of Breakpoint #3 Type of Transaction(s) to - AMD AMD-K6-2/500AFX | Data Sheet - Page 55
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BBB T - AMD AMD-K6-2/500AFX | Data Sheet - Page 56
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 DR3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 - AMD AMD-K6-2/500AFX | Data Sheet - Page 57
more information about the RDMSR and WRMSR instructions, see the AMD K86™ Family BIOS and Software Tools Development Guide, order# 21062. MCAR and MCTR. The AMD-K6-2 processor does not support the generation of a machine check exception. However, the processor does provide a 64-bit machine check - AMD AMD-K6-2/500AFX | Data Sheet - Page 58
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 63 54 0 MCTR Stamp Counter. Wi t h e a ch p ro c e s s o r c l o ck cy c l e , t h e processor increments the 64-bit time stamp counter (TSC) MSR. Figure 33 shows the format of the TSC. 63 0 TSC Figure 33. Time - AMD AMD-K6-2/500AFX | Data Sheet - Page 59
(EFER) contains the control bits that enable the extended features of the AMD-K6-2 processor. Figure 34 shows the format of the EFER register, and Table 6 STAR register. For more information, see the SYSCALL and SYSRET Instruction Specification Application Note, order# 21086. 63 48 47 32 31 - AMD AMD-K6-2/500AFX | Data Sheet - Page 60
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 7. SYSCALL/ Figure 36. Write Handling Control Register (WHCR)-Model 8/[7:0] Memory Management Registers The AMD -K 6-2 processor controls segm ented m emory management with the registers listed in Table 8. Figure - AMD AMD-K6-2/500AFX | Data Sheet - Page 61
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Global and Interrupt Descriptor Table Registers 47 32-Bit Linear Base Address Local Descriptor Table Register and Task Register 63 32-Bit Linear - AMD AMD-K6-2/500AFX | Data Sheet - Page 62
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Task State Segment 31 Figure 38 shows the format of the task state segment (TSS). I/O Permission Bitmap (IOPB) ( - AMD AMD-K6-2/500AFX | Data Sheet - Page 63
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Paging The AMD-K6-2 processor can physically address up to four Gbytes of memory. This memory can be segmented into pages. The size of these pages is determined by the - AMD AMD-K6-2/500AFX | Data Sheet - Page 64
AMD-K6®-2 Processor Data Sheet Preliminary Information 4-Mbyte Page Frame Page Directory 21850J/0-February 2000 PDE CR3 Physical Address 31 22 21 0 Page Directory Offset Page Offset Linear - AMD AMD-K6-2/500AFX | Data Sheet - Page 65
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 31 Page Table Base Address Symbol Description Bits AVL Available to Software 11-9 Reserved 8 PS Page Size 7 Reserved 6 A Accessed 5 PCD Page Cache Disable 4 - AMD AMD-K6-2/500AFX | Data Sheet - Page 66
the descriptor points. The system segment descriptor is used to point to a task state segment, a call gate, or a local descriptor table. The AMD-K6-2 processor uses gates to transfer control between executable segments with different privilege levels. Figure 46 on page 49 shows the format of the - AMD AMD-K6-2/500AFX | Data Sheet - Page 67
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Reserved Symbol G D AVL P DPL DT Type Description Granularity 32-Bit/16-Bit Available to Software Present/Valid Bit Descriptor Privilege Level Descriptor Type - AMD AMD-K6-2/500AFX | Data Sheet - Page 68
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Reserved Symbol G X AVL P DPL DT Type Description Granularity Not Needed Availability to Software Present/Valid Bit Descriptor Privilege - AMD AMD-K6-2/500AFX | Data Sheet - Page 69
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Reserved Symbol P DPL DT a reference to missing page 16 Floating-Point Error Arithmetic error generated by floating-point instruction 17 Alignment Check Data reference to an unaligned operand. (The AC flag and the - AMD AMD-K6-2/500AFX | Data Sheet - Page 70
Application Note, order# 21329. Table 12 lists the MSRs and the corresponding value of the ECX register. Table 12. AMD-K6®-2 Processor Model 8/[F:8] MSRs Model-Specific Register Value of ECX Machine Check Address Register (MCAR) 00h Machine Check Type Register (MCTR) 01h Test Register 12 - AMD AMD-K6-2/500AFX | Data Sheet - Page 71
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 63 43 210 DS EWBEC P C EE SCE) R/W SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions. For more information on EWBEC, see "EWBE Control" on page 201. Write Handling Control Register - AMD AMD-K6-2/500AFX | Data Sheet - Page 72
this MSR to all zeros. Figure 48. Write Handling Control Register (WHCR)-Model 8/[F:8] UC/WC Cacheability Control Register (UWCCR) The AMD-K6-2 processor Model 8/[F:8] provides two variablerange Memory Type Range Registers (MTRRs)-MTRR0 and MTRR1-that each specify a range of memory. Each range - AMD AMD-K6-2/500AFX | Data Sheet - Page 73
State Observability Register (PSOR) Page Flush/Invalidate Register (PFIR) The AMD-K6-2 processor Model 8/[F:8] contains the Page Flush/Invalidate Register (PFIR) (see Figure 51) that allows cache invalidation and optional flushing of a specific 4-Kbyte page from the linear address space. For more - AMD AMD-K6-2/500AFX | Data Sheet - Page 74
Data Sheet Preliminary Information 21850J/0-February 2000 3.3 Instructions Supported by the AMD-K6®-2 Processor This section documents all of the x86 instructions supported by the AMD-K6-2 processor. The following tables show the instruction mnemonic, opcode, modR/M byte, decode type, and - AMD AMD-K6-2/500AFX | Data Sheet - Page 75
and 6 are documented as mm (memory form), mm can only be 10b, 01b or 00b. The fifth column lists the type of instruction decode - short, long, and vector. The AMD-K6-2 processor decode logic can process two short, one long, or one vector decode per clock. The sixth column lists the type of RISC86 - AMD AMD-K6-2/500AFX | Data Sheet - Page 76
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic ADC EAX, imm16/32 ADC mreg8, imm8 ADC mem8, imm8 ADC mreg16/32, imm16/32 ADC mem16/32, imm16/32 ADC mreg16/32, imm8 ( - AMD AMD-K6-2/500AFX | Data Sheet - Page 77
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic AND mreg8, imm8 AND mem8, imm8 AND mreg16/32, imm16/32 AND mem16/32, imm16/32 AND mreg16/32, imm8 (signed ext.) AND mem16/ - AMD AMD-K6-2/500AFX | Data Sheet - Page 78
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic BTS mreg16/32, reg16/32 BTS mem16/32, reg16/32 BTS mreg16/32, imm8 BTS mem16/32, imm8 CALL full pointer CALL near imm16/ - AMD AMD-K6-2/500AFX | Data Sheet - Page 79
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic First Byte CMPSD mem32, mem32 A7h CMPXCHG mreg8, reg8 0Fh CMPXCHG mem8, reg8 0Fh CMPXCHG mreg16/32, reg16/32 0Fh CMPXCHG mem16/32, reg16/ - AMD AMD-K6-2/500AFX | Data Sheet - Page 80
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic First Byte IMUL reg16/32, mem16/32, imm16/32 69h IMUL reg16/32, imm8 (sign extended) 6Bh IMUL reg16/32, mreg16/32, imm8 (signed) - AMD AMD-K6-2/500AFX | Data Sheet - Page 81
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic JNO short disp8 JNB/JAE short disp8 JZ/JE short disp8 JNZ/JNE short disp8 JBE/JNA short disp8 JNBE/JA short disp8 JS - AMD AMD-K6-2/500AFX | Data Sheet - Page 82
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic JMP disp8 (short) JMP far mreg32 (indirect) JMP far mem32 (indirect) JMP near mreg16/32 (indirect) JMP near mem16/32 (indirect) LAHF LAR reg16/ - AMD AMD-K6-2/500AFX | Data Sheet - Page 83
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic MOV mreg16/32, reg16/32 MOV mem16/32, reg16/32 MOV reg8, mreg8 MOV reg8, mem8 MOV reg16/32, mreg16/32 MOV reg16/32, - AMD AMD-K6-2/500AFX | Data Sheet - Page 84
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic MOV mem16/32, imm16/32 MOV reg32, CR0 MOV reg32, CR2 MOV reg32, CR3 MOV reg32, CR4 MOV CR0, reg32 MOV CR2, reg32 MOV - AMD AMD-K6-2/500AFX | Data Sheet - Page 85
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic OR mreg8, reg8 OR mem8, reg8 OR mreg16/32, reg16/32 OR mem16/32, reg16/32 OR reg8, mreg8 OR reg8, mem8 OR reg16/ - AMD AMD-K6-2/500AFX | Data Sheet - Page 86
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic POP ESI POP EDI POP mreg 16/32 POP mem 16/32 POPA/POPAD POPF/POPFD PUSH ES PUSH CS PUSH FS PUSH GS - AMD AMD-K6-2/500AFX | Data Sheet - Page 87
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic RCL mem16/32, 1 RCL mreg8, CL RCL mem8, CL RCL mreg16/32, CL RCL mem16/32, CL RCR mreg8, imm8 RCR mem8, imm8 RCR - AMD AMD-K6-2/500AFX | Data Sheet - Page 88
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic ROL mreg16/32, CL ROL mem16/32, CL ROR mreg8, imm8 ROR mem8, imm8 ROR mreg16/32, imm8 ROR mem16/32, imm8 ROR mreg8, 1 - AMD AMD-K6-2/500AFX | Data Sheet - Page 89
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic SBB reg8, mem8 SBB reg16/32, mreg16/32 SBB reg16/32, mem16/32 SBB AL, imm8 SBB EAX, imm16/32 SBB mreg8, imm8 SBB - AMD AMD-K6-2/500AFX | Data Sheet - Page 90
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic SETNS mem8 SETP/SETPE mreg8 SETP/SETPE mem8 SETNP/SETPO mreg8 SETNP/SETPO mem8 SETL/SETNGE mreg8 SETL/SETNGE mem8 SETNL/SETGE mreg8 SETNL/ - AMD AMD-K6-2/500AFX | Data Sheet - Page 91
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic SHR mreg16/32, 1 SHR mem16/32, 1 SHR mreg8, CL SHR mem8, CL SHR mreg16/32, CL SHR mem16/32, CL SHLD mreg16/32, reg16/ - AMD AMD-K6-2/500AFX | Data Sheet - Page 92
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 14. Integer Instructions (continued) Instruction Mnemonic SUB reg16/32, mem16/32 SUB AL, imm8 SUB EAX, imm16/32 SUB mreg8, imm8 SUB mem8, imm8 SUB mreg16/32, imm16/32 SUB - AMD AMD-K6-2/500AFX | Data Sheet - Page 93
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 14. Integer Instructions (continued) Instruction Mnemonic XCHG reg8, mem8 XCHG reg16/32, mreg16/32 XCHG reg16/32, mem16/32 XCHG EAX, EAX XCHG EAX, ECX XCHG EAX, EDX XCHG EAX, - AMD AMD-K6-2/500AFX | Data Sheet - Page 94
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 15. Floating-Point Instructions Instruction Mnemonic First Second ModR/M Decode Byte Byte Byte Type RISC86 Operations Note F2XM1 D9h F0h short float FABS D9h F1h short float FADD ST(0), ST(i) - AMD AMD-K6-2/500AFX | Data Sheet - Page 95
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 15. Floating-Point Instructions (continued) Instruction Mnemonic First Second ModR/M Decode Byte Byte Byte Type RISC86 Operations Note FDIVR ST(0), mem32real D8h mm-111-xxx short fload, float FDIVR ST - AMD AMD-K6-2/500AFX | Data Sheet - Page 96
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 15. Floating-Point Instructions (continued) Instruction Mnemonic First Second ModR/M Decode Byte Byte Byte Type RISC86 Operations Note FLD mem32real D9h mm-000-xxx short fload, float FLD mem64real DDh - AMD AMD-K6-2/500AFX | Data Sheet - Page 97
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 15. Floating-Point Instructions (continued) Instruction Mnemonic First Second ModR/M Decode Byte Byte Byte Type RISC86 Operations Note FST mem32real D9h mm-010-xxx short fstore FST mem64real DDh mm- - AMD AMD-K6-2/500AFX | Data Sheet - Page 98
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 16. MMX™ Instructions Instruction Mnemonic Prefix First ModR/M Decode RISC86 Byte(s) Byte Byte Type Operations Note EMMS 0Fh 77h vector MOVD mmreg, mreg32 0Fh 6Eh 11-xxx-xxx short - AMD AMD-K6-2/500AFX | Data Sheet - Page 99
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 16. MMX™ Instructions (continued) Instruction Mnemonic Prefix First ModR/M Decode RISC86 Byte(s) Byte Byte Type Operations Note PANDN mmreg1, mmreg2 0Fh DFh 11-xxx-xxx short meu PANDN mmreg, mem64 - AMD AMD-K6-2/500AFX | Data Sheet - Page 100
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 16. MMX™ Instructions (continued) Instruction Mnemonic Prefix First ModR/M Decode RISC86 Byte(s) Byte Byte Type Operations Note PSRAD mmreg1, mmreg2 0Fh E2h 11-xxx-xxx short meu PSRAD mmreg, mem64 - AMD AMD-K6-2/500AFX | Data Sheet - Page 101
and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched. 2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2 processor, this instruction performs in the same manner as the PREFETCH - AMD AMD-K6-2/500AFX | Data Sheet - Page 102
and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched. 2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2 processor, this instruction performs in the same manner as the PREFETCH - AMD AMD-K6-2/500AFX | Data Sheet - Page 103
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4 Signal Descriptions 4.1 Signal Terminology The following terminology is used in this chapter: s Driven-The processor actively pulls the signal up to the High-voltage state or pulls the signal down to the Low- - AMD AMD-K6-2/500AFX | Data Sheet - Page 104
A20M# A[31:3] AP ADS# ADSC# APCHK# BE[7:0]# EADS# HIT# HITM# INV D/C# EWBE# LOCK# M/IO# NA# SCYC W/R# CACHE# KEN# PCD PWT WB/WT# AMD-K6®-2 Processor FERR# IGNNE# FLUSH# INIT INTR NMI RESET SMI# SMIACT# STPCLK# Data and Data Parity Inquire Cycles Floating-Point Error Handling External Interrupts - AMD AMD-K6-2/500AFX | Data Sheet - Page 105
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.2 Summary Sampled A20M# (Address Bit 20 Mask) Input A20M# is used to simulate the behavior of the 8086 when running in Real mode. The assertion of A20M # causes the processor to force bit 20 of the physical address - AMD AMD-K6-2/500AFX | Data Sheet - Page 106
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.3 A[31:3] (Address Bus) Summary Driven, Sampled, and Floated A[31:5] Bidirectional, A[4:3] Output A[31:3] contain the physical address for the current bus cycle. The processor drives addresses on A[31:3] during - AMD AMD-K6-2/500AFX | Data Sheet - Page 107
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.4 ADS# (Address Strobe) Summary asserted, ADS# is only driven in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. The processor floats ADS # off the clock edge that BOFF - AMD AMD-K6-2/500AFX | Data Sheet - Page 108
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.6 Summary Sampled AHOLD (Address Hold) Input AHOLD can be asserted by the system to initiate one or more inquire cycles. To allow the system to drive the address bus during an inquire cycle, the processor floats A[31 - AMD AMD-K6-2/500AFX | Data Sheet - Page 109
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.7 AP (Address Parity) Summary system logic must respond appropriately to the assertion of this signal. As an Output: The processor drives AP valid off the clock edge on which ADS# is asserted until the clock edge - AMD AMD-K6-2/500AFX | Data Sheet - Page 110
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.8 Summary Driven APCHK# (Address Parity Check) Output If the processor detects an address parity error during an inquire cycle, APCHK# is asserted for one clock. The processor does not take an internal exception as - AMD AMD-K6-2/500AFX | Data Sheet - Page 111
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.9 BE[7:0]# (Byte Enables) Summary Output BE[7:0]# are used by the processor to indicate the valid data bytes during a write cycle and the requested data bytes during a read cycle. The byte enables can be used to - AMD AMD-K6-2/500AFX | Data Sheet - Page 112
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.10 Summary Sampled BF[2:0] (Bus Frequency) Inputs, Internal Pullups BF[2:0] determine the internal operating frequency of the processor. The frequency of the CLK input signal is multiplied internally by a ratio - AMD AMD-K6-2/500AFX | Data Sheet - Page 113
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.11 Summary Sampled BOFF# (Backoff) Input If BOFF # is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state by floating the following signals: A[31:3], ADS - AMD AMD-K6-2/500AFX | Data Sheet - Page 114
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.12 Summary Sampled BRDY# (Burst Ready) Input, Internal Pullup BRDY# is asserted to the processor by system logic to indicate either that the data bus is being driven with valid data during a read cycle or that the - AMD AMD-K6-2/500AFX | Data Sheet - Page 115
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.13 Summary Sampled BRDYC# (Burst Ready Copy) Input, Internal Pullup BRDYC # has the identical function as BRDY #. In the event BRDY # becomes too - AMD AMD-K6-2/500AFX | Data Sheet - Page 116
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.14 Summary Driven BREQ (Bus Request) Output BREQ is asserted by the processor to request the bus in order to complete an internally pending bus cycle. The system logic can use BREQ to arbitrate among the bus - AMD AMD-K6-2/500AFX | Data Sheet - Page 117
Information AMD-K6®-2 Processor Data Sheet 4.16 Summary Sampled CLK (Clock) Input The CLK signal is the bus clock for the processor and is the reference for all signal timings under normal operation (except for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal frequency multiplier applied - AMD AMD-K6-2/500AFX | Data Sheet - Page 118
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.18 D[63:0] (Data Bus) Summary Driven, Sampled, and Floated Bidirectional D[63:0] represent the processor's 64-bit data bus. Each of the eight bytes of data that comprise this bus is qualified as valid by its - AMD AMD-K6-2/500AFX | Data Sheet - Page 119
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.19 DP[7:0] (Data For systems that do not support data parity, DP[7:0] should be connected to VCC3 through pullup resistors. As Outputs: For single-transfer write cycles, the processor drives DP[7:0] with valid parity - AMD AMD-K6-2/500AFX | Data Sheet - Page 120
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.20 Summary Sampled AHOLD or BOFF# is asserted by the system logic in order to execute a cache inquire cycle, the processor begins sampling EADS # two clock edges after AHOLD or BOFF # is sampled asserted. If the system - AMD AMD-K6-2/500AFX | Data Sheet - Page 121
in the processor's cache s The decode and execution of an instruction that follows a currently-executing serializing instruction s The assertion or special cycle. On the AMD-K6-2 Model 8/[F:8] processor, if EFER[3] is set to 1, then EWBE # is ignored by the processor. For more information on the - AMD AMD-K6-2/500AFX | Data Sheet - Page 122
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.22 Summary Driven FERR# (Floating-Point Error) Output The assertion of FERR # indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point instruction. This signal - AMD AMD-K6-2/500AFX | Data Sheet - Page 123
/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.23 Summary Sampled FLUSH# (Cache Flush) Input In response to sampling FLUSH# asserted, the processor writes back any data cache lines that are in the modified state, invalidates all lines in the instruction and data caches - AMD AMD-K6-2/500AFX | Data Sheet - Page 124
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.24 Summary Driven HIT# (Inquire Cycle Hit) Output The processor asserts HIT# during an inquire cycle to indicate that the cache line is valid within the processor's instruction or data cache (also known as a cache - AMD AMD-K6-2/500AFX | Data Sheet - Page 125
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.26 Summary Driven 4.27 Summary Sampled Chapter 4 HLDA (Hold Acknowledge) Output When HOLD is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts HLDA in an - AMD AMD-K6-2/500AFX | Data Sheet - Page 126
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.28 Summary IGNNE# (Ignore -point instruction during the execution of a floating-point instruction, MMX instruction, 3DNow! instruction, or the WAIT instruction- hereafter referred to as the target instruction. If - AMD AMD-K6-2/500AFX | Data Sheet - Page 127
/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Sampled The processor samples IGNNE # as instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMX state, Model-Specific - AMD AMD-K6-2/500AFX | Data Sheet - Page 128
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.30 Summary Sampled INTR (Maskable Interrupt) Input INTR is the system's maskable interrupt input to the processor. When the processor samples and recognizes INTR asserted, the processor the processor's instruction or - AMD AMD-K6-2/500AFX | Data Sheet - Page 129
2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.32 Summary Sampled KEN# (Cache Enable) Input If KEN # is sampled asserted, it indicates that the address presented by the processor is cacheable. If KEN # is sampled asserted and the processor intends to perform a cache-line fill - AMD AMD-K6-2/500AFX | Data Sheet - Page 130
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.33 LOCK# (Bus Lock) Output Summary The processor asserts LOCK# accesses s Page Directory and Page Table accesses s XCHG instruction s An instruction with an allowable LOCK prefix In order to ensure that locked - AMD AMD-K6-2/500AFX | Data Sheet - Page 131
/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.34 M/IO# (Memory or I/O) Summary Driven and Floated Output The processor drives M/IO# during a bus cycle to indicate whether it is addressing the memory or I/O space. If M/IO# = 1, the processor is addressing memory or - AMD AMD-K6-2/500AFX | Data Sheet - Page 132
is predefined. If NMI is sampled asserted while the processor is executing the interrupt service routine for a previous NMI, the subsequent NMI remains pending until the completion of the execution of the IRET instruction at the end of the interrupt service routine. NMI is sampled and latched as - AMD AMD-K6-2/500AFX | Data Sheet - Page 133
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.37 PCD (Page Cache Disable) Output Summary The processor drives PCD to indicate the operating system's specification of cacheability for the page being addressed. System logic can use PCD to control external - AMD AMD-K6-2/500AFX | Data Sheet - Page 134
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.38 Summary Driven PCHK# (Parity Check) Output The processor asserts except in the Tri-State Test mode. For each BRDY# returned to the processor during a read cycle with a parity error detected on the data bus, PCHK - AMD AMD-K6-2/500AFX | Data Sheet - Page 135
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.39 PWT (Page Writethrough) Output Summary The processor drives PWT to indicate the operating system's specification of the writeback state or writethrough state for the page being addressed. PWT, together with WB/ - AMD AMD-K6-2/500AFX | Data Sheet - Page 136
3DNow! state, and all registers, and then the processor jumps to address FFFF_FFF0h to start instruction specification before it is negated. During a warm reset, while CLK and VCC are within their specification , the normal operation of the AMD-K6-2 processor is not adversely affected in any - AMD AMD-K6-2/500AFX | Data Sheet - Page 137
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.42 SCYC (Split Cycle) Output Summary The processor asserts SCYC during misaligned, locked transfers on the D[63:0] data bus. The processor generates additional bus cycles to complete the transfer of misaligned - AMD AMD-K6-2/500AFX | Data Sheet - Page 138
AMD-K6®-2 Processor is not recognized until the next instruction boundary. If SMI# is to be recognized on the instruction boundary associated with a BRDY#, it the SMM service routine is exited. 4.44 Summary Driven SMIACT# (System Management Interrupt Active) Output The processor acknowledges the - AMD AMD-K6-2/500AFX | Data Sheet - Page 139
AMD-K6®-2 Processor Data Sheet 4.45 Summary Sampled STPCLK# (Stop Clock) Input, Internal Pullup The assertion of STPCLK# causes the processor to enter the Stop Grant state, during which the processor the processor performs the following actions, in the order shown: 1. Flushes its instruction - AMD AMD-K6-2/500AFX | Data Sheet - Page 140
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Sampled The processor always samples TCK, except while TRST# is asserted. 4.47 Summary Sampled TDI (Test Data Input) Input, Internal Pullup TDI is the serial test data and instruction input for boundary-scan testing - AMD AMD-K6-2/500AFX | Data Sheet - Page 141
Information AMD-K6®-2 Processor Data core voltage requirements for 2.9 V and 3.2 V products (High) or 2.2 V and 2.4 V products (Low). VCC2H/L# always equals 0 and is never floated for 2.2 V and 2.4 V products-even during the Tri-State Test mode. To ensure proper operation for 2.9V and 3.2V - AMD AMD-K6-2/500AFX | Data Sheet - Page 142
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 samples VCC2H/L# should Test mode. 4.53 W/R# (Write/Read) Output Summary Driven and Floated The processor drives W/R# to indicate whether it is performing a write or a read cycle on the bus. In addition, W/R# is - AMD AMD-K6-2/500AFX | Data Sheet - Page 143
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.54 Summary Sampled WB/WT# ( writeback cycle-as the result of an inquire cycle, an internal snoop, a flush operation, or the WBINVD instruction. WB/WT# is sampled on the clock edge that the first BRDY# or NA# of a bus - AMD AMD-K6-2/500AFX | Data Sheet - Page 144
transition of RESET and can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met relative to the clock edge before the negation of RESET. 8. On the AMD-K6-2 processor Model 8/[F:8], if EFER[3] is set to 1, then EWBE# is ignored by the - AMD AMD-K6-2/500AFX | Data Sheet - Page 145
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 21. Output Pin Float Conditions Name Floated At: (Note 1) Note Name Floated At: (Note 1) Note A[4:3] HLDA, AHOLD, BOFF# 2, 3 HLDA Always Driven ADS# - AMD AMD-K6-2/500AFX | Data Sheet - Page 146
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 24. Bus Cycle Definition Bus Cycle Initiated Code Read, Instruction Cache Line Fill Code Read, Noncacheable Code Read, Noncacheable Encoding for Special Cycle Interrupt Acknowledge I/O Read I/O Write Memory Read, - AMD AMD-K6-2/500AFX | Data Sheet - Page 147
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 5 Bus Cycles The following cycle. A clock extends from one rising CLK edge to the next rising CLK edge. The processor samples and drives most signals relative to the rising edge of CLK. The exceptions to this rule - AMD AMD-K6-2/500AFX | Data Sheet - Page 148
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Waveform Description Don't care or bus is driven Signal or bus is changing from Low to High Signal - AMD AMD-K6-2/500AFX | Data Sheet - Page 149
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 5.2 Bus State Machine Diagram Addr Data Trans Transition No Last BRDY# Asserted? Yes Yes No Bus Transition? Note: The processor transitions to the IDLE state on the clock edge on which BOFF# or RESET is sampled - AMD AMD-K6-2/500AFX | Data Sheet - Page 150
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Idle Address Data Data-NA# Requested Pipeline Address The processor does not drive the system bus in the Idle state and remains in this state until a new bus cycle is requested. The processor enters this state off the - AMD AMD-K6-2/500AFX | Data Sheet - Page 151
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Pipeline Data Transition sampled asserted). If the last BRDY# is not sampled asserted, the processor enters the Pipeline Data state. If the processor samples the last BRDY# asserted in this state, it determines if a - AMD AMD-K6-2/500AFX | Data Sheet - Page 152
AMD-K6-2 processor performs single or burst memory bus cycles. The single-transfer memory bus cycle transfers 1, 2, 4, or 8 bytes and requires a minimum of two clocks. Misaligned instructions during the BRDY# to indicate its support for cacheability. The processor (which drives CACHE#) and the system - AMD AMD-K6-2/500AFX | Data Sheet - Page 153
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BREQ D[63:0] DP[7:0] CACHE# EWBE# KEN# BRDY# WB/WT# Read Cycle Write Cycle Write Cycle (Next Cycle Delayed - AMD AMD-K6-2/500AFX | Data Sheet - Page 154
, it determines the appropriate pair of bus cycles-each with its own ADS# and BRDY# - required to complete the access. The AMD-K6-2 processor performs misaligned memory reads and memory writes using least-significant bytes (LSBs) first followed by most-significant bytes (MSBs). Table 26 shows the - AMD AMD-K6-2/500AFX | Data Sheet - Page 155
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] BRDY# Memory Read (Misaligned) Memory Write (Misaligned) ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA - AMD AMD-K6-2/500AFX | Data Sheet - Page 156
burst read cycles and a pipelined burst read cycle. The AMD-K6-2 processor drives CACHE# and ADS# together to specify that the current bus cycle is a burst cycle. If the processor samples KEN# asserted with the first BRDY#, it performs burst transfers. During the burst transfers, the system logic - AMD AMD-K6-2/500AFX | Data Sheet - Page 157
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# NA# D[63:0] CACHE# KEN# BRDY# Burst Read Burst Read Pipelined Burst Read ADDR DATA DATA DATA DATA IDLE - AMD AMD-K6-2/500AFX | Data Sheet - Page 158
. The AMD-K6-2 processor initiates writebacks under the following conditions: s Replacement-If a cache-line fill is initiated for a cache line currently filled with valid entries, the processor selects a line for replacement based on a least-recently-used (LRU) algorithm for the instruction cache - AMD AMD-K6-2/500AFX | Data Sheet - Page 159
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# CACHE# M/IO# D/C# W/R# D[63:0] KEN# BRDY# WB/WT# Burst Read Burst Writeback from L1 Cache ADDR DATA DATA DATA DATA - AMD AMD-K6-2/500AFX | Data Sheet - Page 160
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 5.4 I/O Read and Write Basic I/O Read and Write The processor accesses I/O when it executes an I/O instruction (for example, IN or OUT). Figure 59 shows an I/O read followed by an I/O write. The processor drives M/IO - AMD AMD-K6-2/500AFX | Data Sheet - Page 161
and Write Table 28 shows the misaligned I/O read and write cycle order executed by the AMD-K6-2 processor. In Figure 60, the least-significant bytes (LSBs) are transferred first. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to transfer the most-significant - AMD AMD-K6-2/500AFX | Data Sheet - Page 162
Cycle The AMD-K6-2 processor provides built-in level-one data and instruction caches. Each performs writebacks to memory. An inquire cycle can be initiated by asserting AHOLD, BOFF#, or HOLD. AHOLD is exclusively used to support inquire cycles. During AHOLD-initiated inquire cycles, the processor - AMD AMD-K6-2/500AFX | Data Sheet - Page 163
February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] HOLD HLDA BRDY# HOLD on every clock edge but does not assert HLDA until any in-progress cycle or sequence of locked cycles is completed. When the processor samples HOLD negated - AMD AMD-K6-2/500AFX | Data Sheet - Page 164
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 HOLD-Initiated Inquire Hit to Shared or Exclusive Line Figure 62 shows a HOLD-initiated inquire cycle. In this example, the processor samples HOLD asserted during the burst memory read cycle. The processor completes - AMD AMD-K6-2/500AFX | Data Sheet - Page 165
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# HOLD HLDA EADS# INV Burst Memory Read Figure 62. HOLD-Initiated Inquire Hit to Shared or Exclusive Line Inquire Chapter 5 Bus Cycles 145 - AMD AMD-K6-2/500AFX | Data Sheet - Page 166
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 HOLD-Initiated Inquire Hit to Modified Line Figure 63 shows the same sequence as Figure 62, but in Figure 63 the inquire cycle hits a modified line and the processor asserts both HIT# and HITM#. In this example, the - AMD AMD-K6-2/500AFX | Data Sheet - Page 167
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# HOLD HLDA EADS# INV Burst Memory Read Inquire Figure 63. HOLD-Initiated Inquire - AMD AMD-K6-2/500AFX | Data Sheet - Page 168
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD-Initiated Inquire Miss AHOLD can be asserted by the system to initiate one or more inquire cycles. To allow the system to drive the address bus during an inquire cycle, the processor floats A[31:3] and AP off the - AMD AMD-K6-2/500AFX | Data Sheet - Page 169
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Read CLK A[31:3] BE[7:0]# AP APCHK# ADS# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV Figure 64. AHOLD-Initiated Inquire Miss Inquire Chapter 5 Bus Cycles 149 - AMD AMD-K6-2/500AFX | Data Sheet - Page 170
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD-Initiated Inquire Hit to Shared or Exclusive Line In Figure 65, the processor negated. If the inquire cycle hits a modified line, the processor performs a writeback cycle before it drives a new bus cycle. The - AMD AMD-K6-2/500AFX | Data Sheet - Page 171
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV Burst Memory Read Inquire Figure 65. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line Chapter 5 Bus Cycles 151 - AMD AMD-K6-2/500AFX | Data Sheet - Page 172
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD-Initiated Inquire Hit to Modified Line Figure 66 shows an AHOLD-initiated inquire cycle that hits a modified line. During the inquire cycle in this example, the processor asserts both HIT# and HITM# on the clock - AMD AMD-K6-2/500AFX | Data Sheet - Page 173
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV Burst Memory Read Inquire Figure 66. AHOLD-Initiated Inquire Hit to Modified Line Writeback Chapter 5 Bus Cycles 153 - AMD AMD-K6-2/500AFX | Data Sheet - Page 174
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD Restriction When the system logic drives an AHOLD-initiated inquire cycle, it must assert AHOLD for at least two clocks before it asserts EADS#. This requirement guarantees the processor recognizes and responds - AMD AMD-K6-2/500AFX | Data Sheet - Page 175
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK ADS# W/R# HITM# EADS# D[63:0] BRDY# Legal AHOLD negation during write cycle AHOLD Illegal AHOLD negation during write cycle The system must ensure - AMD AMD-K6-2/500AFX | Data Sheet - Page 176
AMD-K6®-2 Processor problems that arise as a result of inquire cycles. The processor samples BOFF# on every clock edge. If BOFF# is sampled asserted, the processor a modified line, the processor performs a writeback cycle before it restarts the aborted cycle. If the processor samples BOFF# asserted on - AMD AMD-K6-2/500AFX | Data Sheet - Page 177
21850J/0-February 2000 Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BOFF# D[63:0] BRDY# Figure 68. BOFF# Timing Preliminary Information AMD-K6®-2 Processor Data Sheet Back Off Cycle Restart Read Cycle Chapter 5 Bus Cycles 157 - AMD AMD-K6-2/500AFX | Data Sheet - Page 178
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Locked Cycles Basic Locked Operation The processor asserts LOCK# Table accesses s Page Directory and Page Table accesses s XCHG instruction s An instruction with an allowable LOCK prefix In order to ensure that locked - AMD AMD-K6-2/500AFX | Data Sheet - Page 179
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# LOCK# M/IO# D/C# W/R# SCYC D[63:0] BRDY# Locked Read Cycle Locked Write Cycle ADDR DATA DATA DATA IDLE IDLE ADDR DATA - AMD AMD-K6-2/500AFX | Data Sheet - Page 180
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Locked Operation with BOFF# Intervention Figure 70 shows BOFF# asserted within a locked read-write pair of bus cycles. In this example, the processor asserts LOCK# with ADS# to drive a locked memory read cycle followed - AMD AMD-K6-2/500AFX | Data Sheet - Page 181
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# LOCK# M/IO# D/C# W/R# BOFF# D[63:0] BRDY# Locked Read Cycle Aborted Write Cycle Figure 70. Locked Operation with BOFF# Intervention Restart Write Cycle Chapter 5 Bus Cycles 161 - AMD AMD-K6-2/500AFX | Data Sheet - Page 182
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Interrupt Acknowledge In response to recognizing the system's maskable interrupt (INTR), the processor drives an interrupt acknowledge cycle at the next instru cti on boundary. Dur ing an inter rupt acknowledge cycle, - AMD AMD-K6-2/500AFX | Data Sheet - Page 183
21850J/0-February 2000 CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# LOCK# INTR D[63:0] KEN# BRDY# Preliminary Information AMD-K6®-2 Processor Data Sheet Interrupt Acknowledge Cycles Interrupt Number Figure 71. Interrupt Acknowledge Operation Chapter 5 Bus Cycles 163 - AMD AMD-K6-2/500AFX | Data Sheet - Page 184
Information 21850J/0-February 2000 5.6 Special Bus Cycles The AMD-K6-2 processor drives special bus cycles that include stop grant, 30). A halt special cycle is generated after the processor executes the HLT instruction. If the processor samples FLUSH# asserted, it writes back any data cache - AMD AMD-K6-2/500AFX | Data Sheet - Page 185
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BRDY# A[4:3] = 00b FBh Halt Cycle Figure 72. Basic Special Bus Cycle (Halt Cycle) Chapter 5 Bus Cycles 165 - AMD AMD-K6-2/500AFX | Data Sheet - Page 186
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Shutdown Cycle CLK A[31:3] BE[7:0]# ADS FEh). The system logic must assert NMI, INIT, RESET, or SMI# to get the processor out of the shutdown state. Shutdown Occurs (Triple Fault) Shutdown Special Cycle A[4:3] = 00b - AMD AMD-K6-2/500AFX | Data Sheet - Page 187
Preliminary Information AMD-K6®-2 Processor Data Sheet Stop Grant and Stop Clock States Figure 74 and Figure 75 show the processor transition from normal the next instruction retirement boundary, the processor performs the following actions, in the order shown: 1. Its instruction pipelines are - AMD AMD-K6-2/500AFX | Data Sheet - Page 188
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# CACHE# STPCLK# D[63:0] KEN# BRDY# STPCLK# Sampled Asserted Stop Grant Special Cycle Stop - AMD AMD-K6-2/500AFX | Data Sheet - Page 189
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Stop Clock CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# CACHE# STPCLK# D[63:0] KEN# BRDY# Stop Grant State STPCLK# Sampled Negated Normal (Re-entered after PLL - AMD AMD-K6-2/500AFX | Data Sheet - Page 190
of its internal state, and branch to address FFFF_FFF0h-the same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMX state, Model-Specific Registers (MSRs), the CD and NW bits of the CR0 register - AMD AMD-K6-2/500AFX | Data Sheet - Page 191
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] KEN# BRDY# INIT INIT Sampled Asserted Code Fetch FFFF_FFF0h Figure 76. INIT-Initiated Transition from Protected Mode to Real Mode Chapter 5 Bus Cycles 171 - AMD AMD-K6-2/500AFX | Data Sheet - Page 192
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 172 Bus Cycles Chapter 5 - AMD AMD-K6-2/500AFX | Data Sheet - Page 193
system logic must reset the AMD-K6-2 processor by asserting the RESET signal. When the processor samples RESET asserted, it RESET, the processor unconditionally runs its Built-In Self Test (BIST), performs the normal reset functions, then jumps to address FFFF_FFF0h to start instruction execution. ( - AMD AMD-K6-2/500AFX | Data Sheet - Page 194
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 6.2 RESET Requirements During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification. (See "CLK Switching Characteristics" on page 267 for - AMD AMD-K6-2/500AFX | Data Sheet - Page 195
FPU Instruction Pointer 0000_0000_0000h 3 FPU Data Pointer 0000_0000_0000h 3 FPU Opcode Register 000_0000_0000b 3 Notes: 1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful. If EAX is non-zero, BIST failed. 2. EDX contains the AMD-K6-2 processor - AMD AMD-K6-2/500AFX | Data Sheet - Page 196
BIST was successful. If EAX = 0000_0000h, BIST was successful. If EAX is non-zero, BIST failed. 2. EDX contains the AMD-K6-2 processor signature, where X indicates the processor Stepping ID. 3. The contents of these registers are preserved following the recognition of INIT. 4. The CD and NW bits of - AMD AMD-K6-2/500AFX | Data Sheet - Page 197
Preliminary Information AMD-K6®-2 Processor Data Sheet 6.4 State of Processor After INIT The recognition of the assertion of INIT causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address FFFF_FFF0h-the same instruction execution starting - AMD AMD-K6-2/500AFX | Data Sheet - Page 198
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 178 Power-on Configuration and Initialization Chapter 6 - AMD AMD-K6-2/500AFX | Data Sheet - Page 199
sections describe the basic architecture and resources of the AMD-K6-2 processor internal caches. The performance of the AMD-K6-2 processor is enhanced by a writeback level-one (L1) cache. The cache is organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache, each with two - AMD AMD-K6-2/500AFX | Data Sheet - Page 200
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 The processor cache design takes 31 Byte 30 Byte 30 Byte 0 2 MESI Bits Byte 0 2 MESI Bits Note: Instruction-cache lines have only two coherency states (valid or invalid) rather than the four MESI coherency - AMD AMD-K6-2/500AFX | Data Sheet - Page 201
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet each instruction byte. The predecode bits indicate the number of bytes to the start of the next x86 instruction. The predecode bits are passed with the instruction bytes to the decoders where they assist with parallel - AMD AMD-K6-2/500AFX | Data Sheet - Page 202
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 occurs, the cache is updated but an external memory update does not occur. If a data line is in - AMD AMD-K6-2/500AFX | Data Sheet - Page 203
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 35 describes how the CACHE# signal is driven based on the cycle type, the CI bit of TR12, the PCD signal, and the UWCCR model-specific register. Table 35. CACHE# Signal Generation Cycle Type CI Bit of TR12 PCD - AMD AMD-K6-2/500AFX | Data Sheet - Page 204
INVD instruction can be AMD-K6-2 processor Model 8/[F:8] (see "PFIR" on page 195). Unlike the previous two methods of flushing the caches, this particular method requires the software to be aware of which specific pages must be flushed and invalidated. 7.5 Cache-Line Fills The processor performs - AMD AMD-K6-2/500AFX | Data Sheet - Page 205
AMD-K6®-2 Processor Data Sheet 7.6 Chapter 7 The processor does not cache certain memory accesses such as locked operations. In addition, the processor and task switches occur, some cache lines eventually require replacement. Instruction cache lines are replaced using a Least Recently Used (LRU) - AMD AMD-K6-2/500AFX | Data Sheet - Page 206
write hits to the write-allocated cache line is high. The following is a description of three mechanisms by which the AMD-K6-2 processor performs write allocations. A write allocate is performed when any one or more of these mechanisms indicates that a pending write is to a cacheable area of memory - AMD AMD-K6-2/500AFX | Data Sheet - Page 207
2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Write to a Sector Write Allocate Limit 63 When the processor performs a cache line multiplied by 4 Mbytes, defines an upper memory limit. Any pending write cycle that addresses memory below this limit causes the processor to perform - AMD AMD-K6-2/500AFX | Data Sheet - Page 208
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 (assuming the address is not within a range where write allocates are disallowed). Write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is - AMD AMD-K6-2/500AFX | Data Sheet - Page 209
1 Mbyte (000A_0000h to 000F_FFFFh) because it is considered a noncacheable region of memory. For AMD-K6-2 processor Model 8/[F:8], if a memory region is defined as write-combinable or uncacheable by a MTRR, write allocates are not performed in that region. Figure 81 shows the logic flow for all the - AMD AMD-K6-2/500AFX | Data Sheet - Page 210
cycle addresses a region of memory defined as write combinable or uncacheable by an MTRR, write allocates are not performed in that region. MTRRs are only supported in the AMD-K6-2 processor Model 8/[F:8]. For all other steppings, treat this condition as equal to 0. 5. Write to a Cacheable Page (CCR - AMD AMD-K6-2/500AFX | Data Sheet - Page 211
2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 6. Write to a Sector-A write allocate is performed if the address of If the address is less than the limit, write allocate for that memory address is performed as long as conditions 8 through 10 do not prevent write allocate (even if - AMD AMD-K6-2/500AFX | Data Sheet - Page 212
2000 7.8 Prefetching Hardware Prefetching The AMD-K6-2 processor conditionally performs cache prefetching which results in the The PREFETCH instruction format is defined in Table 17, "3DNow!™ Instructions," on page 81. For more detailed information, see the 3DNow!™ Technology Manual, order - AMD AMD-K6-2/500AFX | Data Sheet - Page 213
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 36. Data Cache States for Read and Write Accesses Cache State After Access Type Cache State Before Access Access Type1 MESI State8 - AMD AMD-K6-2/500AFX | Data Sheet - Page 214
AMD-K6®-2 Processor Data performed with INV equal to 0 (non-invalidating) and INV equal to 1 (invalidating)-snoops, and invalidations. Internal snooping is initiated by the processor (rather than system logic) during certain cache accesses. It is used to maintain coherency between the instruction - AMD AMD-K6-2/500AFX | Data Sheet - Page 215
modified state and then marks all lines in the instruction and data caches as invalid. The AMD-K6-2 processor Model 8/[F:8] processor contains the Page Flush/Invalidate Register (PFIR) that allows cache invalidation and optional flushing of a specific 4-Kbyte page from the linear address space (see - AMD AMD-K6-2/500AFX | Data Sheet - Page 216
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 WBINVD and INVD Cache-Line Replacement PF. If an attempt to invalidate or flush a page results in a page fault, the processor sets the PF bit to 1, and the invalidate or flush operation is not performed instructions - AMD AMD-K6-2/500AFX | Data Sheet - Page 217
shared or exclusive modified - writeback to bus INVD Instruction - - Notes: All writebacks are 32-byte burst write cycles. - Not applicable or none. * The AMD-K6-2 processor Model 8/[F:8] supports the PFIR. Cache State After Operation MESI State INV=0 INV=1 INV=0 INV=1 shared invalid - AMD AMD-K6-2/500AFX | Data Sheet - Page 218
AMD-K6-2 processor and the resources that are snooped. Table 38. Snoop Action Snooping Action Type of Event Type of Access Instruction . Then the instruction cache performs a burst read from memory. 3. If an internal snoop hits a line in the instruction cache, the instruction cache line is - AMD AMD-K6-2/500AFX | Data Sheet - Page 219
writeback apply to two related concepts in a read-write cache like the AMD-K6-2 processor L1 data cache. The following conditions apply to both the writethrough and s Inquire cycles s The FLUSH# signal s Writing to the PFIR (AMD-K6-2/[F:8] only) s The WBINVD instruction Cache Organization 199 - AMD AMD-K6-2/500AFX | Data Sheet - Page 220
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 200 Cache Organization Chapter 7 - AMD AMD-K6-2/500AFX | Data Sheet - Page 221
AMD-K6®-2 Processor Data Sheet 8 Write Merge Buffer The AMD-K6-2 processor Model 8/[F:8] contains an 8-byte write merge buffer that allows the processor single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. 8.1 EWBE Control - AMD AMD-K6-2/500AFX | Data Sheet - Page 222
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 s EFER[2] is defined as the Speculative EWBE Disable (SEWBED). SEWBED only affects the processor when GEWBED equals 0. If GEWBED equals 0 and SEWBED equals 1, the processor write ordering and performance. For more - AMD AMD-K6-2/500AFX | Data Sheet - Page 223
Registers UC/WC Cacheability Control Register (UWCCR) The AMD-K6-2 processor Model 8/[F:8] provides two variablerange Memory Type Range Registers a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. This memory type is - AMD AMD-K6-2/500AFX | Data Sheet - Page 224
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 . Symbol with both the physical base address field of the UWCCR register and the physical address generated by the processor. If the results of the two AND operations are equal, then the generated physical address is - AMD AMD-K6-2/500AFX | Data Sheet - Page 225
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Chapter 8 Table 40. WC/UC Memory Type WCn 0 1 0 or 1 UCn Memory Type 0 No effect on cacheability or write combining 0 Write-combining memory range ( - AMD AMD-K6-2/500AFX | Data Sheet - Page 226
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 41. Valid Masks and Range Sizes (continued) Masks 111_1111_1000_0000b 111_1111_0000_0000b 111_1110_0000_0000b 111_1100_0000_0000b 111_1000_0000_0000b 111_0000_0000_0000b 110_0000_0000_0000b 100_0000_0000_0000b - AMD AMD-K6-2/500AFX | Data Sheet - Page 227
To increase performance, the processor is designed to simultaneously decode most floating-point instructions with most short-decodeable instructions. See "Software Environment" on page 21 for a description of the floating-point data types, registers, and instructions. The AMD-K6-2 processor provides - AMD AMD-K6-2/500AFX | Data Sheet - Page 228
the floating-point exception and continues instruction execution. When the processor negates FERR#, the external logic negates IGNNE#. See "FERR# (Floating-Point Error)" on page 102 and "IGNNE# (Ignore Numeric Exception)" on page 106 for more details. AMD-K6®-2 Processor FERR# I/O Address Port F0h - AMD AMD-K6-2/500AFX | Data Sheet - Page 229
are pipelined for higher performance. To increase performance, the processor is designed to simultaneously decode all MMX and 3DNow! instructions with most other instructions. For more information on MMX instructions, see the AMD-K6® Processor Multimedia Technology Manual, order# 20726. For more - AMD AMD-K6-2/500AFX | Data Sheet - Page 230
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 instruction, MMX instruction, 3DNow! instruction or WAIT instruction. The sampling of IGNNE# asserted only affects processor o p e ra t i o n d u r i n g t h e ex e c u t i o n o f a n e r ro r -s e n s i t ive f l oa t - AMD AMD-K6-2/500AFX | Data Sheet - Page 231
AMD-K6®-2 Processor Data Sheet 10 System Management Mode (SMM) 10.1 10.2 Overview SMM is an alternate operating mode entered by way of a system management interrupt (SMI#) and handled by an interrupt service address, and stack sizes, although instruction prefixes can override these defaults s - AMD AMD-K6-2/500AFX | Data Sheet - Page 232
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 s Far jumps or calls cannot transfer control to a to 0003_FFFFh) contain a fill-down SMM state-save area. The default entry point for the SMM service routine is 0003_8000h. 212 System Management Mode (SMM) Chapter 10 - AMD AMD-K6-2/500AFX | Data Sheet - Page 233
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Fill Down SMM State-Save Area 0003_FFFFh 0003_FE00h 32-Kbyte Minimum RAM Service Routine Entry Point SMM Service Routine 0003_8000h SMM Base Address (CS) 0003_0000h Figure 85. SMM Memory Table 42 shows the - AMD AMD-K6-2/500AFX | Data Sheet - Page 234
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 10.3 214 SMM State-Save Area When the processor acknowledges an SMI# in the SMM state-save area relative to the SMM base address. The SMM service routine can alter any of the read/write values in the state-save area. - AMD AMD-K6-2/500AFX | Data Sheet - Page 235
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Chapter 10 Table 43. SMM State-Save Area Map (continued) Address Offset Contents Saved FFA4h I/O Trap Dword FFA0h - FF9Ch I/O Trap EIP* FF98h - FF94h - - AMD AMD-K6-2/500AFX | Data Sheet - Page 236
that are available on the processor. The SMM revision identifier fields are as follows: s Bits 31-18-Reserved s Bit 17-SMM base address relocation (1 = enabled) s Bit 16-I/O trap restart (1 = enabled) s Bits 15-0- SMM revision level for the AMD-K6-2 processor = 0002h 216 System Management Mode - AMD AMD-K6-2/500AFX | Data Sheet - Page 237
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 44 shows the format of to by the SMM service routine to specify whether the return from SMM takes the processor back to the Halt state or to the next instruction after the HLT instruction. Chapter 10 System - AMD AMD-K6-2/500AFX | Data Sheet - Page 238
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 10.7 218 return to Halt state 0 = return to next instruction after the HLT instruction If the return from SMM takes the processor back to the Halt state, the HLT instruction is not re-executed, but the Halt special bus - AMD AMD-K6-2/500AFX | Data Sheet - Page 239
Preliminary Information AMD-K6®-2 Processor Data Sheet 10.8 Chapter 10 The I/O trap dword is related to the I/O trap restart slot (see "I/O Trap Restart Slot"). If bit 1 of the I/O trap dword is set by the processor, it means that SMI# was asserted during the execution of an I/O instruction. The - AMD AMD-K6-2/500AFX | Data Sheet - Page 240
never has bit 1 of the I/O trap dword set, and the second SMM service routine must not rewrite the I/O trap restart slot. During a simultaneous SMI# I/O instruction trap and debug breakpoint trap, the AMD-K6-2 processor first responds to the SMI# and postpones recognizing the debug exception until - AMD AMD-K6-2/500AFX | Data Sheet - Page 241
Test and Debug The AMD-K6-2 processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. In addition, the debug features of the processor allow designers to debug the instruction execution of software components - AMD AMD-K6-2/500AFX | Data Sheet - Page 242
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 11.2 Tri-State Test Mode The Tri-State Test mode causes the processor to float its output and bidirectional pins, which is useful for board-level manufacturing testing. In this mode, the processor processor core - AMD AMD-K6-2/500AFX | Data Sheet - Page 243
logic circuits, such as boards containing a processor. The AMD-K6-2 processor supports the TAP standard defined in the IEEE Standard states and their definition. s Instruction Register (IR)-The IR contains the instructions that select the test operation to be performed and the Test Data Register ( - AMD AMD-K6-2/500AFX | Data Sheet - Page 244
page 253 and "Signal Switching Characteristics" on page 267 to obtain the electrical specifications of the test signals. The AMD-K6-2 processor provides an Instruction Register (IR) and three Test Data Registers (TDR) to support the boundary-scan architecture. The IR and one of the TDRs-the Boundary - AMD AMD-K6-2/500AFX | Data Sheet - Page 245
IR shift register in the Update-IR state, and the current instruction is defined by the IR output register. See "TAP Instructions" on page 231 for a list and definition of the instructions supported by the AMD-K6-2 processor. Boundary Scan Register (BSR). The BSR is a Test Data Register consisting - AMD AMD-K6-2/500AFX | Data Sheet - Page 246
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 While in the the contents of the BSR shift register in the Update-DR state. If the current instruction is EXTEST, the processor's output pins, as well as those bidirectional pins that are enabled as outputs, are driven - AMD AMD-K6-2/500AFX | Data Sheet - Page 247
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 47. Boundary Scan Bit Definitions for Model 8/[7:0] Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable - AMD AMD-K6-2/500AFX | Data Sheet - Page 248
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 47. Boundary Scan Bit Definitions for Model 8/[7:0] (continued) Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable - AMD AMD-K6-2/500AFX | Data Sheet - Page 249
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 48. Boundary Scan Bit Definitions for Model 8/[F:8] Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable - AMD AMD-K6-2/500AFX | Data Sheet - Page 250
AMD-K6®-2 Processor Data instruction. The fields of the DIR and their values are shown in Table 49 and are defined as follows: s Version Code-This 4-bit field is incremented by AMD manufacturing for each major revision of silicon. s Part Number-This 16-bit field identifies the specific processor - AMD AMD-K6-2/500AFX | Data Sheet - Page 251
reduces test time. The BR register is selected by the BYPASS and HIGHZ instructions as well as by any instructions not supported by the AMD-K6-2 processor. TAP Instructions The processor supports the three instructions required by the IEEE 1149.1 standard - EXTEST, SAMPLE/PRELOAD, and BYPASS - as - AMD AMD-K6-2/500AFX | Data Sheet - Page 252
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 TAP Controller State Machine SAMPLE/PRELOAD. The SAMPLE/PRELOAD instruction performs two functions. These functions are as follows: s During the Capture-DR state, the processor loads the BSR shift register with the - AMD AMD-K6-2/500AFX | Data Sheet - Page 253
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Test-Logic-Reset 1 0 Run-Test/Idle 1 0 0 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 1 1 1 Select-IR-Scan 1 0 Capture-IR 0 Shift-IR 0 1 1 Exit1- - AMD AMD-K6-2/500AFX | Data Sheet - Page 254
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 The states of the TAP controller are described as follows: Test-Logic-Reset. This state represents the initial reset state of the TAP controller and is entered when the processor EXTEST instruction, the processor loads - AMD AMD-K6-2/500AFX | Data Sheet - Page 255
shifting following the exit from the Pause-IR state. L1 Cache Inhibit The AMD-K6-2 processor provides a means for inhibiting the normal operation of its L1 instruction and data caches while still supporting an external cache. This capability allows system designers to disable the L1 cache during - AMD AMD-K6-2/500AFX | Data Sheet - Page 256
Executing the WBINVD instruction s Executing the INVD instruction (modified cache lines are not written back to memory) s Make use of the Page Flush/Invalidate Register (PFIR) (AMD-K6-2/[F:8] only)(see "PFIR" on page 195) 11.5 Debug Debug Registers The AMD-K6-2 processor implements the standard - AMD AMD-K6-2/500AFX | Data Sheet - Page 257
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Symbol LEN 3 R/W 3 LEN 2 R/W 2 LEN 1 R/W 1 LEN 0 R/W 0 Description Bits Length of Breakpoint #3 31-30 Type of Transaction(s) to Trap 29-28 Length of Breakpoint #2 27- - AMD AMD-K6-2/500AFX | Data Sheet - Page 258
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 - AMD AMD-K6-2/500AFX | Data Sheet - Page 259
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet DR3 31 30 29 28 27 26 25 24 23 22 21 20 19 and are compared to the linear addresses of processor cycles to determine if a breakpoint occurs. Debug register DR7 defines the specific type of cycle that must occur in order - AMD AMD-K6-2/500AFX | Data Sheet - Page 260
AMD-K6®-2 Processor exception does not occur for that breakpoint. If the processor decodes an instruction that writes or reads DR7 through DR0, the BD specific task. When set to 1, G3-G0 globally enable breakpoints 3 through 0, respectively. Unlike L3-L0, G3-G0 are not set to 0 whenever the processor - AMD AMD-K6-2/500AFX | Data Sheet - Page 261
AMD-K6®-2 Processor Data Sheet Debug Exceptions The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the operation of the processor and are provided in order to be software compatible with previous generations of x86 processors Bits Breakpoint 00b 00b2 Instruction Execution 00b One- - AMD AMD-K6-2/500AFX | Data Sheet - Page 262
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Interrupt 01h. The following events are considered debug traps that cause the processor INT 3 instruction is defined in the x86 architecture as a breakpoint instruction. This instruction causes the processor to generate - AMD AMD-K6-2/500AFX | Data Sheet - Page 263
AMD-K6®-2 Processor Data Sheet 12 Clock Control The AMD-K6-2 processor supports five modes of clock control. The processor can transition between these modes to maximize performance the successful execution of the HLT instruction. During this state, the internal processor clock is stopped. s Stop - AMD AMD-K6-2/500AFX | Data Sheet - Page 264
Data Sheet Preliminary Information 21850J/0-February 2000 12.1 Halt State Enter Halt State During the execution of the HLT instruction, the AMD-K6-2 processor executes a Halt special cycle. After BRDY# is sampled asserted during this cycle, and then EWBE# is also sampled asserted (if not - AMD AMD-K6-2/500AFX | Data Sheet - Page 265
After recognizing the assertion of STPCLK#, the AMD-K6-2 processor flushes its instruction pipelines, completes all pending and in-progress Halt state in that the processor disables most of its internal clock distribution in the Stop Grant state. In order to support the following operations, the - AMD AMD-K6-2/500AFX | Data Sheet - Page 266
cache line, the processor performs a writeback cycle. Following the completion of any writeback, the processor returns to the state from which it entered the Stop Grant Inquire state. 12.4 Stop Clock State Enter Stop Clock State If the CLK signal is stopped while the AMD-K6-2 processor is in the - AMD AMD-K6-2/500AFX | Data Sheet - Page 267
AMD-K6®-2 Processor Data Sheet Exit Stop Clock State The AMD-K6-2 processor returns to the Stop Grant state from the Stop Clock state after the CLK signal is started and the internal PLL has stabilized. PLL stabilization is achieved after the CLK signal has been running within its specification - AMD AMD-K6-2/500AFX | Data Sheet - Page 268
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 HLT Instruction RESET, SMI#, INIT, or INTR Asserted Normal Mode - Real - Virtual-8086 - Protected - SMM STPCLK# Asserted STPCLK# Negated, or RESET Asserted Halt State EADS# Asserted Writeback - AMD AMD-K6-2/500AFX | Data Sheet - Page 269
/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 13 Power and Grounding 13.1 Power Connections The AMD-K6-2 processor is a dual voltage device. Two separate supply voltages are required: VCC2 and VCC3. VCC2 provides the core voltage for the processor and VCC3 provides the - AMD AMD-K6-2/500AFX | Data Sheet - Page 270
C13 C26 C28 C31 C16 CC7 C10 13.2 VCC3 (I/O) Plane VCC2 (Core) Plane CC1 CC2 Figure 92. Suggested Component Placement Decoupling Recommendations In addition recommendations about the specific value, quantity, and location of the capacitors, see the AMD-K6® Processor Power Supply Design - AMD AMD-K6-2/500AFX | Data Sheet - Page 271
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 13.3 Pin Connection Requirements For proper operation, the following requirements for signal pin connections must be met: s Do not drive address and data - AMD AMD-K6-2/500AFX | Data Sheet - Page 272
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 252 Power and Grounding Chapter 13 - AMD AMD-K6-2/500AFX | Data Sheet - Page 273
AMD-K6-2/333AFR s AMD-K6-2/450AHX s AMD-K6-2/366AFR s AMD-K6-2/300AFR s AMD-K6-2/400AFQ s AMD-K6-2/350AFR s AMD-K6-2/266AFR Note: The electrical specifications for the AMD-K6-2/400AFR OPN are provided in "Electrical Data for OPN Suffixes AGR, AFX, and 400AFR" on page 258. The AMD-K6-2 processor - AMD AMD-K6-2/500AFX | Data Sheet - Page 274
the AMD-K6-2 processor are shown in Table 54. Table 54. DC Characteristics for OPN Suffixes AHX, 400AFQ, and AFR Symbol This specification applies to components using a CLK frequency of 66 MHz. 9. This specification applies to components using a CLK frequency of 95 MHz. 10. This specification - AMD AMD-K6-2/500AFX | Data Sheet - Page 275
2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 54. DC Characteristics for OPN Suffixes AHX, 400AFQ, and AFR (continued) Symbol Parameter Description Preliminary Data Min Max Comments 7.35 A 266 MHz, Note 2, 8 8.45 A 300 MHz, Note 2, 8, 10 9.40 A 333 MHz, Note - AMD AMD-K6-2/500AFX | Data Sheet - Page 276
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 54. DC Characteristics for OPN Suffixes AHX, 400AFQ, and AFR (continued) Symbol Parameter Description Preliminary Data Min Max Comments COUT I/O Capacitance 20 pF CCLK CLK Capacitance 10 pF CTIN Test - AMD AMD-K6-2/500AFX | Data Sheet - Page 277
power dissipation of the AMD-K6-2 processor during normal and reduced power states. Table 55. Typical and Maximum Power Dissipation for OPN Suffixes AHX, 400AFQ, and AFR Clock Control State 266 300 333 350 MHz6 MHz6,8 MHz6,7 MHz8 366 MHz6 380 400 450 MHz7 MHz6,8 MHz8 475 MHz7 Notes Thermal - AMD AMD-K6-2/500AFX | Data Sheet - Page 278
s AMD-K6-2/533AFX s AMD-K6-2/500AFX s AMD-K6-2/475AFX s AMD-K6-2/450AFX s AMD-K6-2/400AFR Note: The electrical specifications for all frequencies of the OPN suffix AFR other than 400 MHz are provided in "Electrical Data for OPN Suffixes AHX, 400AFQ, and AFR" on page 253. The AMD-K6-2 processor is - AMD AMD-K6-2/500AFX | Data Sheet - Page 279
, the VPIN voltage must never exceed 4.0 V. DC Characteristics The DC characteristics of the AMD-K6-2 processor are shown in Table 58. Table 58. DC Characteristics for OPN Suffixes AGR, AFX, and 400AFR Symbol Parameter Description Preliminary Data Min Max Comments VIL Input Low Voltage - AMD AMD-K6-2/500AFX | Data Sheet - Page 280
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 58. DC Characteristics for OPN Suffixes AGR, AFX, and 400AFR (continued) Symbol Parameter Description Preliminary Data Min Max Comments 10.00 A 400 MHz, Note 2, 8, 10 11.25 A 450 MHz, Note 2, 10 2.2 V - AMD AMD-K6-2/500AFX | Data Sheet - Page 281
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 58. DC Characteristics for OPN Suffixes AGR, AFX, and 400AFR (continued) Symbol Parameter Description Preliminary Data Min Max Comments CTCK TCK Capacitance 10 pF Notes: 1. VCC3 refers to the voltage - AMD AMD-K6-2/500AFX | Data Sheet - Page 282
the typical and maximum power dissipation of the AMD-K6-2 processor during normal and reduced power states. Table 59. Typical and Maximum Power Dissipation for OPN Suffixes AGR, AFX, and 400AFR Clock Control State 400 450 MHz6,8 MHz8 475 MHz7 500 533 550 MHz8 MHz9,10 MHz8 Notes Thermal Power - AMD AMD-K6-2/500AFX | Data Sheet - Page 283
the two possible drive strength configurations supported by the AMD-K6-2 processor. These two models are called the Standard I/O Model and the Strong I/O Model. AMD developed the two models to allow system designers to perform analog simulations of AMD-K6-2 processor signals that interface with the - AMD AMD-K6-2/500AFX | Data Sheet - Page 284
the normal operating range of the AMD-K6-2 processor for those simulators that yield more accurate results based on this wider range. Figure 93 and Figure 94 on page 265 illustrate the min/typ/max pulldown and pullup V/I curves for K6STD between 0V and 3.3V. s The rising and falling ramp rates - AMD AMD-K6-2/500AFX | Data Sheet - Page 285
to the AMD-K6® Processor I/O Model (IBIS) Application Note, order# 21084. 15.4 I/O Buffer AC and DC Characteristics See "Signal Switching Characteristics" on page 267 for the AMD-K6-2 processor AC timing specifications. See "Electrical Data" on page 253 for the AMD-K6-2 processor DC specifications - AMD AMD-K6-2/500AFX | Data Sheet - Page 286
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 266 I/O Buffer Characteristics Chapter 15 - AMD AMD-K6-2/500AFX | Data Sheet - Page 287
AMD-K6-2 processor signal switching characteristics are presented in Table 61 through Table 70. Valid delay, float, setup, and hold timing specifications are listed. These specifications of the CLK input to the AMD-K6-2 processor for 100-MHz and 66-MHz bus operation, respectively, as measured - AMD AMD-K6-2/500AFX | Data Sheet - Page 288
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.2 Clock Switching Characteristics for 100-MHz Bus Operation Table 61. CLK Switching Characteristics for 100-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure Comments Frequency - AMD AMD-K6-2/500AFX | Data Sheet - Page 289
analyze hold times to the system logic. The setup and hold time requirements for the AMD-K6-2 processor input signals must be met by the system logic to assure the proper operation of the AMD-K6-2 processor. The setup and hold timings during functional and boundary-scan test mode are given relative - AMD AMD-K6-2/500AFX | Data Sheet - Page 290
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.5 Output Delay Timings for 100-MHz Bus Operation Table 63. Output Delay Timings for 100-MHz Bus Operation Symbol Parameter Description t6 A[31:3] Valid Delay t7 A[31:3] Float Delay t8 ADS# Valid Delay t9 - AMD AMD-K6-2/500AFX | Data Sheet - Page 291
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 63. Output Delay Timings for 100-MHz Bus Operation (continued) Symbol Parameter Description Preliminary Data Min Max Figure t34 PCD Valid Delay t35 PCD Float Delay t36 PCHK# Valid Delay t37 PWT - AMD AMD-K6-2/500AFX | Data Sheet - Page 292
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation Table 64. Input Setup and Hold Timings for 100-MHz synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met - AMD AMD-K6-2/500AFX | Data Sheet - Page 293
Preliminary Information AMD-K6®-2 Processor Data Sheet Table 64. Input Setup and Hold Timings for 100-MHz Bus Operation -sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they - AMD AMD-K6-2/500AFX | Data Sheet - Page 294
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.7 Output Delay Timings for 66-MHz Bus Operation Table 65. Output Delay Timings for 66-MHz Bus Operation Symbol Parameter Description t6 A[31:3] Valid Delay t7 A[31:3] Float Delay t8 ADS# Valid Delay t9 - AMD AMD-K6-2/500AFX | Data Sheet - Page 295
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 65. Output Delay Timings for 66-MHz Bus Operation (continued) Symbol Parameter Description Preliminary Data Min Max Figure t34 PCD Valid Delay t35 PCD Float Delay t36 PCHK# Valid Delay t37 PWT - AMD AMD-K6-2/500AFX | Data Sheet - Page 296
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation Table 66. Input Setup and Hold Timings for 66-MHz synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met - AMD AMD-K6-2/500AFX | Data Sheet - Page 297
2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 66. Input Setup and Hold Timings for 66-MHz Bus Operation -sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, - AMD AMD-K6-2/500AFX | Data Sheet - Page 298
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.9 RESET and Test Signal Timing Table 67. RESET and Configuration Signals for 100-MHz Time 2 clocks 100 Note 2 Notes: 1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge - AMD AMD-K6-2/500AFX | Data Sheet - Page 299
2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 68. RESET and Configuration Signals for 66-MHz Bus Operation t102 FLUSH# Hold Time 2 clocks 100 Note 2 Notes: 1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on - AMD AMD-K6-2/500AFX | Data Sheet - Page 300
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 69. TCK Waveform and TRST# Timing at 25 MHz Symbol Parameter Description Preliminary Data Min Max Figure Comments TCK Frequency 25 MHz 101 t103 TCK Period 40.0 ns 101 t104 TCK High Time 14.0 ns - AMD AMD-K6-2/500AFX | Data Sheet - Page 301
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet WAVEFORM Figure 96. Diagrams Key INPUTS Must be steady Can change from High to Low Can change from Low to High Don't care, - AMD AMD-K6-2/500AFX | Data Sheet - Page 302
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 CLK 1.5 V Tx Tx Tx Tx Output Signal tf Valid tv Min v = 6, 8, 10, 12, 15, 18, 20, 22, 24, - AMD AMD-K6-2/500AFX | Data Sheet - Page 303
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet CLK RESET Tx t90 1.5 V FLUSH# (Synchronous) FLUSH#, BRDYC# (Asynchronous) BF[2:0] (Asynchronous) • • • Tx 1.5 V • • • t92, 93 t91 1.5 V t99 t100 • • • • • • t97, 101 t98, 102 • • • t94 t95 - AMD AMD-K6-2/500AFX | Data Sheet - Page 304
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 t104 2.0 V 1.5 V 0.8 V t107 Figure 101. TCK Waveform t105 t106 t103 t108 1.5 V Figure 102. TRST# Timing TCK TDI, TMS TDO - AMD AMD-K6-2/500AFX | Data Sheet - Page 305
AMD-K6-2 processor thermal specifications for all valid OPN suffixes. Table 71. Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR θJC Junction-Case 1.0 °C/W Maximum Thermal Power 2.2 V Component 2.4 V Component 266 MHz 300 MHz 333 MHz 350 MHz 366 MHz 380 MHz 400 MHz* 450 MHz 475 - AMD AMD-K6-2/500AFX | Data Sheet - Page 306
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 286 Thermal Design Chapter 17 - AMD AMD-K6-2/500AFX | Data Sheet - Page 307
Information AMD-K6®-2 Processor Data Sheet Table 72. Package Thermal Specification for OPN Suffixes AGR, AFX, and 400AFR θJC Junction-Case 1.0 °C/W Maximum Thermal Power 2.2 V Component 2.3 V Component 400 MHz1 450 MHz 475 MHz 500 MHz 533 MHz2 16.90 W 18.80 W 19.80 W 20.75 W 550 MHz 25 - AMD AMD-K6-2/500AFX | Data Sheet - Page 308
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Temperature (Ambient) Thermal Resistance (°C/W) TCA Sink Case θSA θCA θIF Figure 104. Thermal Model Figure 105 illustrates the - AMD AMD-K6-2/500AFX | Data Sheet - Page 309
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet The thermal resistance of a heatsink is determined by the heat dissipation surface area, the material and shape of the heatsink, and the airflow - AMD AMD-K6-2/500AFX | Data Sheet - Page 310
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Thermal grease is recommended Figure 106. Processor Heat Dissipation Path The processor case temperature is measured to ensure that the thermal solution meets the processor's operational specification. This temperature - AMD AMD-K6-2/500AFX | Data Sheet - Page 311
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Thermally Conductive Epoxy Thermocouple Figure 107. Measuring Case Temperature 17.2 Layout and Airflow Considerations Voltage Regulator A voltage regulator is required to support the lower voltage (3.3 V and lower - AMD AMD-K6-2/500AFX | Data Sheet - Page 312
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 A heatsink and fan combination can deliver much better thermal performance than a heatsink alone. More importantly, with a fan/sink the airflow requirements in a system design are not as critical. A unidirectional - AMD AMD-K6-2/500AFX | Data Sheet - Page 313
Information AMD-K6®-2 Processor Data Sheet Main Board Fan P/S V e Drive Bays n t s Fan Vents Front Figure 110. Airflow Path in a Dual-Fan System Figure 111 shows the airflow management in a system using the ATX form-factor. The orientation of the power supply fan and the motherboard are - AMD AMD-K6-2/500AFX | Data Sheet - Page 314
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 For more information about thermal design considerations, see the AMD-K6® Processor Thermal Solution Design Application Note, order# 21085. 294 Thermal Design Chapter 17 - AMD AMD-K6-2/500AFX | Data Sheet - Page 315
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 18 Pin Description Diagram Figure 112. AMD-K6®-2 Processor Top-Side View Chapter 18 Pin Description Diagram 295 - AMD AMD-K6-2/500AFX | Data Sheet - Page 316
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 113. AMD-K6®-2 Processor Pin-Side View 296 Pin Description Diagram Chapter 18 - AMD AMD-K6-2/500AFX | Data Sheet - Page 317
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 19 Pin Designations AMD-K6®-2 Processor Functional Grouping Address Pin Pin Name No. Data Pin Pin Name No. Control Pin Pin Name No. A3 AL-35 D0 K-34 A20M# AK-08 - AMD AMD-K6-2/500AFX | Data Sheet - Page 318
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 298 Pin Designations Chapter 19 - AMD AMD-K6-2/500AFX | Data Sheet - Page 319
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 20 Package Specifications 20.1 321-Pin Staggered CPGA Package Specification Table 73. 321-Pin Staggered CPGA Package Specification Symbol A B C D E F G H M N d e f Min 49.28 45.59 31.01 44.90 2.91 1.30 3.05 0.43 2. - AMD AMD-K6-2/500AFX | Data Sheet - Page 320
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 114. 321-Pin Staggered CPGA Package Specification 300 Package Specifications Chapter 20 - AMD AMD-K6-2/500AFX | Data Sheet - Page 321
/550 /533 /500 /475 /450 /400 /380 /350 /333 /300 /266 Family/Core AMD-K6-2 Table 74. Valid Ordering Part Number Combinations OPN Package Type Operating Voltage Case Temperature AMD-K6-2/550AGR 321-pin CPGA 2.2V-2.4V (Core) 3.135V-3.6V (I/O) 0°C - 70°C AMD-K6-2/533AFX 321-pin CPGA 2.1V-2.3V - AMD AMD-K6-2/500AFX | Data Sheet - Page 322
1V-2.3V (Core) 3.135V-3.6V (I/O) 0°C - 70°C AMD-K6-2/366AFR 321-pin CPGA 2.1V-2.3V (Core) 3.135V-3.6V (I/O) 0°C - 70°C AMD-K6-2/350AFR 321-pin CPGA 2.1V-2.3V (Core) 3.135V-3.6V (I/O) 0°C - 70°C AMD-K6-2/333AFR 321-pin CPGA 2.1V-2.3V (Core) 3.135V-3.6V (I/O) 0°C - 70°C AMD-K6-2/300AFR 321 - AMD AMD-K6-2/500AFX | Data Sheet - Page 323
AMD-K6®-2 Processor Data Sheet Index Numerics 100-MHz Bus 1, 3 clock switching characteristics 268 input setup and hold timings 272 output delay timings 270 321-Pin Staggered CPGA Package 1 specification 299 3DNow transition 131 BYPASS Instruction 232 Bypass Register 231 C Cache 9 - AMD AMD-K6-2/500AFX | Data Sheet - Page 324
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 flush 103 inhibit, L1 235 Registers 34, 236 DR3-DR0 239 DR5-DR4 239 DR6 240 DR7 240 Decode, Instruction 12 Decoders 7 Decoupling Recommendations 250 Descriptions, Signal 83 Design, Thermal 285 Designations, - AMD AMD-K6-2/500AFX | Data Sheet - Page 325
, 160, 194, 197-199, 235, 243 246 miss, AHOLD-initiated 148 Instruction decode 12 fetch 11 pointer 25 prefetch 9 Instructions 3DNow 81, 209 EMMS 14 FEMMS 14 INVD 196 MMX 78, 209 PREFETCH 10, 192 supported by the AMD-K6-2 processor 54 TAP 231 WBINVD 196 Integer Data Types 23 Internal - AMD AMD-K6-2/500AFX | Data Sheet - Page 326
2 enhanced RISC86 6 overview, AMD-K6-2 processor 5 Misaligned I/O read and write 141 single-transfer memory read and write 134 MMX Technology 13-17, 21, 54, 116, 173, 177 exceptions 209 instruction compatibility, floating-point and 209 instructions 78, 210 register operation 8 registers - AMD AMD-K6-2/500AFX | Data Sheet - Page 327
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Prefetching 10, 192 PSOR 50, 53, 175-176 PWT Instruction 115 R Ranges, Operating 253, 258 Ratings, Absolute 254, 259 Read and Write basic I/O 140 misaligned I/O 141 Reads, Burst Reads and Pipelined Burst 136 - AMD AMD-K6-2/500AFX | Data Sheet - Page 328
AMD-K6®-2 Processor 2, 9 Single Instruction Multiple Data (SIMD MHz bus operation 268 66-MHz bus operation 268 input setup and hold timings for 100-MHz bus 272 input setup and hold timings for 66-MHz bus 276 output delay timings for 100-MHz bus 270 output delay timings for 66-MHz specifications - AMD AMD-K6-2/500AFX | Data Sheet - Page 329
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Transition from Protected 267 ranges 264 regulator 291-292 W W/R 122, 263-264 WAE15M 187 WAELIM 187 WB/WT 123 WBINVD Instruction 196 WCDE 40, 187 WHCR 37, 40, 50-51, 176, 187, 191 Write handling control register - AMD AMD-K6-2/500AFX | Data Sheet - Page 330
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 310 Index
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 |
 |
Preliminary Information
AMD-K6-2
Processor
Data Sheet
®