AMD AMD-K6-2/500AFX Data Sheet - Page 59
The EFER register as defined in the Model 8/[7:0] has, changed in the Model 8/[F:8]. See - k6 2 specifications
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Extended Feature Enable Register (EFER)-Model 8[7:0]. Th e ex t e n d e d feature enable register (EFER) contains the control bits that enable the extended features of the AMD-K6-2 processor. Figure 34 shows the format of the EFER register, and Table 6 defines the function of each bit in the EFER register. Note: The EFER register as defined in the Model 8/[7:0] has changed in the Model 8/[F:8]. See "Extended Feature Enable Register (EFER)-Model 8/[F:8]" on page 50. 63 10 S Reserved C E Symbol Description Bit SCE System Call/Return Extension 0 Figure 34. Extended Feature Enable Register (EFER)-Model 8[7:0] Table 6. Extended Feature Enable Register (EFER)-Model 8[7:0]Definition Bit Description R/W 63-1 Reserved R 0 System Call Extension (SCE) R/W SYSCALL/SYSRET Target Address Register (STAR). The SYSCALL/SYSRET target address register (STAR) contains the target EIP address used by the SYSCALL instruction and the 16-bit code and stack segment selector bases used by the SYSCALL and SYSRET instructions. Figure 35 shows the format of the STAR register, and Table 7 on page 40 defines the function of each bit of the STAR register. For more information, see the SYSCALL and SYSRET Instruction Specification Application Note, order# 21086. 63 48 47 32 31 SYSRET CS Selector and SS Selector Base SYSCALL CS Selector and SS Selector Base 0 Target EIP Address Figure 35. SYSCALL/SYSRET Target Address Register (STAR) Chapter 3 Software Environment 39