AMD AMD-K6-2/500AFX Data Sheet - Page 289
Valid Delay, Float, Setup, and Hold Timings, Signal Switching Characteristics, AMD-K6
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet t2 2.0 V 1.5 V 0.8 V t5 t3 t4 t1 Figure 95. CLK Waveform 16.4 Valid Delay, Float, Setup, and Hold Timings Valid delay and float timings are given for output signals during functional operation and are given relative to the rising edge of CLK. During boundary-scan testing, valid delay and float timings for output signals are with respect to the falling edge of TCK. The maximum valid delay timings are provided to allow a system designer to determine if setup times to the system logic can be met. Likewise, the minimum valid delay timings are used to analyze hold times to the system logic. The setup and hold time requirements for the AMD-K6-2 processor input signals must be met by the system logic to assure the proper operation of the AMD-K6-2 processor. The setup and hold timings during functional and boundary-scan test mode are given relative to the rising edge of CLK and TCK, respectively. Chapter 16 Signal Switching Characteristics 269