AMD AMD-K6-2/500AFX Data Sheet - Page 225
Write Merge Buffer, AMD-K6, 2 Processor Data Sheet, Memory-Range Restrictions., Table 40.
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Chapter 8 Table 40. WC/UC Memory Type WCn 0 1 0 or 1 UCn Memory Type 0 No effect on cacheability or write combining 0 Write-combining memory range (uncacheable) 1 Uncacheable memory range Memory-Range Restrictions. The following rules regarding the address alignment and size of each range must be adhered to when programming the physical base address and physical address mask fields of the UWCCR register: s The minimum size of each range is 128 Kbytes. s The physical base address must be aligned on a 128-Kbyte boundary. s The physical base address must be range-size aligned. For example, if the size of the range is 1 Mbyte, then the physical base address must be aligned on a 1-Mbyte boundary. s All bits set to 1 in the physical address mask must be contiguous. Likewise, all bits set to 0 in the physical address mask must be contiguous. For example: 111_1111_1100_0000b is a valid physical address mask 111_1111_1101_0000b is invalid Table 41 lists the valid physical address masks and the resulting range sizes that can be programmed in the UWCCR register. Table 41. Valid Masks and Range Sizes Masks 111_1111_1111_1111b 111_1111_1111_1110b 111_1111_1111_1100b 111_1111_1111_1000b 111_1111_1111_0000b 111_1111_1110_0000b 111_1111_1100_0000b Size 128 Kbytes 256 Kbytes 512 Kbytes 1 Mbyte 2 Mbytes 4 Mbytes 8 Mbytes Write Merge Buffer 205