AMD AMD-K6-2/500AFX Data Sheet - Page 102
DNow!™ Instructions continued, Instruction Mnemonic, Prefix, Bytes, Opcode, ModR/M, Decode, RISC86
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 17. 3DNow!™ Instructions (continued) Instruction Mnemonic Prefix Opcode ModR/M Decode Byte(s) Byte Byte Type RISC86 Operations Note PFCMPGE mmreg, mem64 0Fh, 0Fh 90h mm-xxx-xxx short mload, meu PFCMPGT mmreg1, mmreg2 0Fh, 0Fh A0h 11-xxx-xxx short meu PFCMPGT mmreg, mem64 0Fh, 0Fh A0h mm-xxx-xxx short mload, meu PFMAX mmreg1, mmreg2 0Fh, 0Fh A4h 11-xxx-xxx short meu PFMAX mmreg, mem64 0Fh, 0Fh A4h mm-xxx-xxx short mload, meu PFMIN mmreg1, mmreg2 0Fh, 0Fh 94h 11-xxx-xxx short meu PFMIN mmreg, mem64 0Fh, 0Fh 94h mm-xxx-xxx short mload, meu PFMUL mmreg1, mmreg2 0Fh, 0Fh B4h 11-xxx-xxx short meu PFMUL mmreg, mem64 0Fh, 0Fh B4h mm-xxx-xxx short mload, meu PFRCP mmreg1, mmreg2 0Fh, 0Fh 96h 11-xxx-xxx short meu PFRCP mmreg, mem64 0Fh, 0Fh 96h mm-xxx-xxx short mload, meu PFRCPIT1 mmreg1, mmreg2 0Fh, 0Fh A6h 11-xxx-xxx short meu PFRCPIT1 mmreg, mem64 0Fh, 0Fh A6h mm-xxx-xxx short mload, meu PFRCPIT2 mmreg1, mmreg2 0Fh, 0Fh B6h 11-xxx-xxx short meu PFRCPIT2 mmreg, mem64 0Fh, 0Fh B6h mm-xxx-xxx short mload, meu PFRSQIT1 mmreg1, mmreg2 0Fh, 0Fh A7h 11-xxx-xxx short meu PFRSQIT1 mmreg, mem64 0Fh, 0Fh A7h mm-xxx-xxx short mload, meu PFRSQRT mmreg1, mmreg2 0Fh, 0Fh 97h 11-xxx-xxx short meu PFRSQRT mmreg, mem64 0Fh, 0Fh 97h mm-xxx-xxx short mload, meu PFSUB mmreg1, mmreg2 0Fh, 0Fh 9Ah 11-xxx-xxx short meu PFSUB mmreg, mem64 0Fh, 0Fh 9Ah mm-xxx-xxx short mload, meu PFSUBR mmreg1, mmreg2 0Fh, 0Fh AAh 11-xxx-xxx short meu PFSUBR mmreg, mem64 0Fh, 0Fh AAh mm-xxx-xxx short mload, meu PI2FD mmreg1, mmreg2 0Fh, 0Fh 0Dh 11-xxx-xxx short meu PI2FD mmreg, mem64 0Fh, 0Fh 0Dh mm-xxx-xxx short mload, meu PMULHRW mmreg1, mmreg2 0Fh, 0Fh B7h 11-xxx-xxx short meu PMULHRW mmreg1, mem64 0Fh, 0Fh B7h mm-xxx-xxx short mload, meu PREFETCH mem8 0Fh 0Dh mm-000-xxx vector load 1 PREFETCHW mem8 0Fh 0Dh mm-001-xxx vector load 1, 2 Notes: 1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched. 2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2 processor, this instruction performs in the same manner as the PREFETCH instruction. 82 Software Environment Chapter 3