AMD AMD-K6-2/500AFX Data Sheet - Page 70
AMDK6®2 Processor Model 8/[F:8] Registers
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 3.2 AMD-K6®-2 Processor Model 8/[F:8] Registers AMD-K6-2 processor Model 8/[F:8] implements the same seven MSRs as the Model 8/[7:0], but the bits and fields within the EFER and WHCR MSRs are not defined identically. Model 8/[F:8] also supports three additional MSRs: UWCCR, PSOR, and PFIR. For more information, see the AMD-K6® Processor BIOS Design Application Note, order# 21329. Table 12 lists the MSRs and the corresponding value of the ECX register. Table 12. AMD-K6®-2 Processor Model 8/[F:8] MSRs Model-Specific Register Value of ECX Machine Check Address Register (MCAR) 00h Machine Check Type Register (MCTR) 01h Test Register 12 (TR12) 0Eh Time Stamp Counter (TSC) 10h Extended Feature Enable Register (EFER) C000_0080h SYSCALL/SYSRET Target Address Register (STAR) C000_0081h Write Handling Control Register (WHCR) C000_0082h UC/WC Cacheability Control Register (UWCCR) C000_0085h Processor State Observability Register (PSOR) C000_0087h Page Flush/Invalidate Register (PFIR) C000_0088h Extended Feature Enable Register (EFER)-Model 8/[F:8] The Extended Feature Enable Register (EFER) contains the control bits that enable the extended features of the processor. Figure 47 shows the format of the EFER register, and Table 13 on page 51 defines the function of each bit of the EFER register. Note: The EFER register as defined in the Model 8/[7:0] has changed in the Model 8/[F:8]. See "Extended Feature Enable Register (EFER)-Model 8[7:0]" on page 39. 50 Software Environment Chapter 3