AMD AMD-K6-2/500AFX Data Sheet - Page 264
Halt State
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 12.1 Halt State Enter Halt State During the execution of the HLT instruction, the AMD-K6-2 processor executes a Halt special cycle. After BRDY# is sampled asserted during this cycle, and then EWBE# is also sampled asserted (if not masked off), the processor enters the Halt state in which the processor disables most of its internal clock distribution. In order to support the following operations, the internal phase-lock loop (PLL) still runs, and some internal resources are still clocked in the Halt state: s Inquire Cycles: The processor continues to sample AHOLD, BOFF#, and HOLD in order to support inquire cycles that are initiated by the system logic. The processor transitions to the Stop Grant Inquire state during the inquire cycle. After returning to the Halt state following the inquire cycle, the processor does not execute another Halt special cycle. s Flush Cycles: The processor continues to sample FLUSH#. If FLUSH# is sampled asserted, the processor performs the flush operation in the same manner as it is performed in the Normal state. Upon completing the flush operation, the processor executes the Halt special cycle which indicates the processor is in the Halt state. s Time Stamp Counter (TSC): The TSC continues to count in the Halt state. s Signal Sampling: The processor continues to sample INIT, INTR, NMI, RESET, and SMI#. After entering the Halt state, all signals driven by the processor retain their state as they existed following the completion of the Halt special cycle. Exit Halt State The AMD-K6-2 processor remains in the Halt state until it samples INIT, INTR (if interrupts are enabled), NMI, RESET, or SMI# asserted. If any of these signals is sampled asserted, the processor returns to the Normal state and performs the corresponding operation. All of the normal requirements for recognition of these input signals apply within the Halt state. 244 Clock Control Chapter 12