AMD AMD-K6-2/500AFX Data Sheet - Page 292
Input Setup and Hold Timings for 100MHz Bus Operation
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation Table 64. Input Setup and Hold Timings for 100-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure Comments t44 A[31:5] Setup Time 3.0 ns 99 t45 A[31:5] Hold Time 1.0 ns 99 t46 A20M# Setup Time 3.0 ns 99 Note 1 t47 A20M# Hold Time 1.0 ns 99 Note 1 t48 AHOLD Setup Time 3.5 ns 99 t49 AHOLD Hold Time 1.0 ns 99 t50 AP Setup Time 1.7 ns 99 t51 AP Hold Time 1.0 ns 99 t52 BOFF# Setup Time 3.5 ns 99 t53 BOFF# Hold Time 1.0 ns 99 t54 BRDY# Setup Time 3.0 ns 99 t55 BRDY# Hold Time 1.0 ns 99 t56 BRDYC# Setup Time 3.0 ns 99 t57 BRDYC# Hold Time 1.0 ns 99 t58 D[63:0] Read Data Setup Time 1.7 ns 99 t59 D[63:0] Read Data Hold Time 1.5 ns 99 t60 DP[7:0] Read Data Setup Time 1.7 ns 99 t61 DP[7:0] Read Data Hold Time 1.5 ns 99 t62 EADS# Setup Time 3.0 ns 99 t63 EADS# Hold Time 1.0 ns 99 t64 EWBE# Setup Time 1.7 ns 99 t65 EWBE# Hold Time 1.0 ns 99 t66 FLUSH# Setup Time 1.7 ns 99 Note 2 t67 FLUSH# Hold Time 1.0 ns 99 Note 2 Notes: 1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 272 Signal Switching Characteristics Chapter 16