AMD AMD-K6-2/500AFX Data Sheet - Page 195
Power-on Configuration and Initialization, AMD-K6, 2 Processor Data Sheet, Table 32.
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Chapter 6 Table 32. Register State After RESET Register State (hex) Notes GDTR base:0000_0000h limit:0FFFFh IDTR base:0000_0000h limit:0FFFFh TR 0000h LDTR 0000h EIP FFFF_FFF0h EFLAGS 0000_0002h EAX 0000_0000h 1 EBX 0000_0000h ECX 0000_0000h EDX 0000_058Xh 2 ESI 0000_0000h EDI 0000_0000h EBP 0000_0000h ESP 0000_0000h CS F000h SS 0000h DS 0000h ES 0000h FS 0000h GS 0000h FPU Stack R7-R0 0000_0000_0000_0000_0000h 3 FPU Control Word 0040h 3 FPU Status Word 0000h 3 FPU Tag Word 5555h 3 FPU Instruction Pointer 0000_0000_0000h 3 FPU Data Pointer 0000_0000_0000h 3 FPU Opcode Register 000_0000_0000b 3 Notes: 1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful. If EAX is non-zero, BIST failed. 2. EDX contains the AMD-K6-2 processor signature, where X indicates the processor Stepping ID. 3. The contents of these registers are preserved following the recognition of INIT. 4. The CD and NW bits of CR0 are preserved following the recognition of INIT. 5. UWCCR, PSOR, and PFIR are implemented only on AMD-K6-2 processor Model 8/[F:8]. 6. "S" represents the Stepping. "B" represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of RESET. Power-on Configuration and Initialization 175