AMD AMD-K6-2/500AFX Data Sheet - Page 122
FERR# (FloatingPoint Error
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.22 Summary Driven FERR# (Floating-Point Error) Output The assertion of FERR # indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point instruction. This signal is provided to allow the system logic to handle this exception in a manner consistent with IBM-compatible PC/AT systems. See "Handling Floating-Point Exceptions" on page 207 for a system logic implementation that supports floating-point exceptions. The state of the numeric error (NE) bit in CR0 does not affect the FERR # signal. The processor is designed so that FERR # does not glitch, enabling the signal to be used as a clocking source for system logic. The processor asserts FERR # on the instruction boundary of the next floating-point instruction, MMX instruction, 3DNow! instruction, or WAIT instruction that occurs following the fl o a t i ng -po i nt i ns tr u c ti o n t h a t c a u s e d th e u n ma s ke d floating-point exception-that is, FERR# is not asserted at the time the exception occurs. The IGNNE# signal does not affect the assertion of FERR#. FERR # is negated during the following conditions: s Following the successful execution of the floating-point instructions FCLEX, FINIT, FSAVE, and FSTENV s Under certain circumstances, following the successful execution of the floating-point instructions FLDCW, FLDENV, and FRSTOR, which load the floating-point status word or the floating-point control word s Following the falling transition of RESET FERR # is always driven except in the Tri-State Test mode. See "IGNNE# (Ignore Numeric Exception)" on page 106 for more details on floating-point exceptions. 102 Signal Descriptions Chapter 4