AMD AMD-K6-2/500AFX Data Sheet - Page 117

21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.16 Summary Sampled CLK (Clock) Input The CLK signal is the bus clock for the processor and is the reference for all signal timings under normal operation (except for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal frequency multiplier applied to CLK to obtain the processor's core operating frequency. See "BF[2:0] (Bus Frequency)" on page 92 for a list of the processor-to-bus clock ratios. The CLK signal must be stable a minimum of 1.0 ms prior to the negation of RESET to ensure the proper operation of the processor. See "CLK Switching Characteristics" on page 267 for details regarding the CLK specifications. 4.17 D/C# (Data/Code) Output Summary Driven and Floated The processor drives D/C # during a memory bus cycle to indicate whether it is addressing data or executable code. D/C# is also used to define other bus cycles, including interrupt acknowledge and special cycles. See Table 25 on page 126 for more details. D/C# is driven off the same clock edge as ADS# and remains in the same state until the clock edge on which NA # or the last expected BRDY # of the cycle is sampled asserted. D/C # is driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles. D/C # is floated off the clock edge that BOFF # is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD. Chapter 4 Signal Descriptions 97